wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2025-02-03	clk: renesas: r8a779a0: Add ISP core clocks	Niklas Söderlund	1	-0/+4
2025-02-03	clk: renesas: r8a779a0: Add FCPVX clocks	Niklas Söderlund	1	-0/+4
2024-10-01	clk: renesas: Remove duplicate and trailing empty lines	Marek Vasut	1	-1/+0
2024-07-30	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	Geert Uytterhoeven	1	-5/+5
2024-07-30	clk: renesas: r8a779a0: Use defines for PLL control registers	Geert Uytterhoeven	1	-4/+9
2024-07-30	clk: renesas: rcar-gen4: Use defines for common CPG registers	Geert Uytterhoeven	1	-6/+6
2024-07-30	clk: renesas: r8a779a0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-04-23	clk: renesas: r8a779a0: Fix CANFD parent clock	Geert Uytterhoeven	1	-1/+1
2023-05-08	clk: renesas: r8a779a0: Add PWM clock	Wolfram Sang	1	-0/+1
2023-01-26	clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC	Kuninori Morimoto	1	-2/+2
2022-10-26	clk: renesas: r8a779a0: Fix SD0H clock name	Wolfram Sang	1	-1/+1
2022-04-29	clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4	Yoshihiro Shimoda	1	-6/+6
2022-04-13	clk: renesas: Move RPC core clocks	Geert Uytterhoeven	1	-4/+7
2022-01-24	clk: renesas: r8a779a0: Add CANFD module clock	Ulrich Hecht	1	-0/+1
2021-12-08	clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver	Yoshihiro Shimoda	1	-324/+26
2021-11-19	clk: renesas: rcar-gen3: Switch to new SD clock handling	Wolfram Sang	1	-4/+2
2021-11-19	clk: renesas: r8a779a0: Add SDnH clock to V3U	Wolfram Sang	1	-1/+10
2021-10-08	clk: renesas: r8a779a0: Add RPC support	Wolfram Sang	1	-0/+32
2021-09-28	clk: renesas: r8a779a0: Add Z0 and Z1 clock support	Geert Uytterhoeven	1	-0/+158
2021-09-24	clk: renesas: r8a779a0: Add TPU clock	Wolfram Sang	1	-0/+1
2021-07-19	clk: renesas: r8a779a0: Add the DSI clocks	Kieran Bingham	1	-1/+3
2021-07-19	clk: renesas: r8a779a0: Add the DU clock	Kieran Bingham	1	-0/+1
2021-05-11	clk: renesas: r8a779a0: Add ISPCS clocks	Niklas Söderlund	1	-0/+4
2021-03-12	clk: renesas: r8a779a0: Add CMT clocks	Wolfram Sang	1	-0/+4
2021-03-10	clk: renesas: r8a779a0: Add TSC clock	Niklas Söderlund	1	-0/+1
2021-03-10	clk: renesas: r8a779a0: Add TMU clocks	Wolfram Sang	1	-0/+6
2021-01-25	clk: renesas: r8a779a0: Add RAVB clocks	Wolfram Sang	1	-0/+6
2021-01-25	clk: renesas: r8a779a0: Add I2C clocks	Wolfram Sang	1	-0/+7
2021-01-12	clk: renesas: r8a779a0: Add SYS-DMAC clocks	Geert Uytterhoeven	1	-0/+2
2021-01-12	clk: renesas: r8a779a0: Add SDHI support	Wolfram Sang	1	-2/+15
2021-01-12	clk: renesas: r8a779a0: Add MSIOF clocks	Geert Uytterhoeven	1	-0/+6
2021-01-12	clk: renesas: r8a779a0: Add PFC/GPIO clocks	Geert Uytterhoeven	1	-0/+5
2021-01-07	clk: renesas: r8a779a0: Fix parent of CBFUSA clock	Geert Uytterhoeven	1	-1/+1
2021-01-07	clk: renesas: r8a779a0: Remove non-existent S2 clock	Geert Uytterhoeven	1	-1/+0
2021-01-07	clk: renesas: r8a779a0: Add HSCIF support	Wolfram Sang	1	-0/+4
2020-12-28	clk: renesas: r8a779a0: Add RWDT clocks	Wolfram Sang	1	-0/+9
2020-12-28	clk: renesas: r8a779a0: Add VSPX clock support	Kieran Bingham	1	-0/+4
2020-12-28	clk: renesas: r8a779a0: Add VSPD clock support	Kieran Bingham	1	-0/+2
2020-12-28	clk: renesas: r8a779a0: Add FCPVD clock support	Kieran Bingham	1	-0/+2
2020-12-10	clk: renesas: r8a779a0: Fix R and OSC clocks	Geert Uytterhoeven	1	-3/+10
2020-12-10	clk: renesas: r8a779a0: Add VIN clocks	Jacopo Mondi	1	-0/+32
2020-12-10	clk: renesas: r8a779a0: Add CSI4[0-3] clocks	Jacopo Mondi	1	-0/+4
2020-12-10	clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static	Geert Uytterhoeven	1	-1/+1
2020-09-17	clk: renesas: cpg-mssr: Add support for R-Car V3U	Yoshihiro Shimoda	1	-0/+276