Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-07-21 | clk: Convert to using %pOF instead of full_name | 1 | -2/+1 | |
2017-06-07 | clk: sunxi-ng: Support multiple variable pre-dividers | 1 | -5/+5 | |
2017-05-14 | clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset | 1 | -1/+1 | |
2017-03-06 | clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock | 1 | -1/+1 | |
2017-01-02 | clk: sunxi-ng: A31: Fix spdif clock register | 1 | -2/+2 | |
2016-11-21 | clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it | 1 | -1/+1 | |
2016-10-19 | clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent | 1 | -0/+12 | |
2016-09-16 | clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk | 1 | -1/+1 | |
2016-09-16 | clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs | 1 | -10/+10 | |
2016-09-16 | clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks | 1 | -9/+13 | |
2016-08-25 | clk: sunxi-ng: Add A31/A31s clocks | 1 | -0/+1235 |