| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-10-17 | clk: mxl: Fix a clk entry by adding relevant flags |   Rahul Tanwar | 1 | -0/+1 |
| 2022-10-17 | clk: mxl: Add option to override gate clks | Rahul Tanwar | 1 | -0/+1 |
| 2022-10-17 | clk: mxl: Remove redundant spinlocks | Rahul Tanwar | 1 | -6/+0 |
| 2022-10-17 | clk: mxl: Switch from direct readl/writel based IO to regmap based IO | Rahul Tanwar | 1 | -17/+21 |
| 2020-05-26 | clk: intel: Add CGU clock driver for a new SoC |   Rahul Tanwar | 1 | -0/+335 |
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index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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