wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-08-14	clk: mmp: Switch to use kmemdup_array()	Andy Shevchenko	1	-6/+4
2024-08-12	clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags	Abel Vesa	1	-2/+2
2024-08-11	clk: samsung: exynosautov9: add dpum clock support	Kwanghoon Son	1	-0/+83
2024-08-08	clk: hisilicon: Remove unnecessary local variable	Thorsten Blum	1	-4/+3
2024-08-08	clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP	David Virag	1	-6/+16
2024-08-08	clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix	David Virag	1	-1/+1
2024-08-07	clk: at91: sam9x7: add sam9x7 pmc driver	Varshini Rajendran	2	-0/+947
2024-08-07	clk: at91: sama7g5: move mux table macros to header file	Varshini Rajendran	2	-25/+26
2024-08-07	clk: at91: sam9x7: add support for HW PLL freq dividers	Varshini Rajendran	2	-2/+29
2024-08-07	clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs	Varshini Rajendran	4	-6/+21
2024-08-06	clk: use clk_core_unlink_consumer() helper	Nuno Sá	1	-1/+1
2024-08-04	clk: qcom: camcc-sm8150: Correct qcom_cc_really_probe() argument	Bjorn Andersson	1	-1/+1
2024-08-02	clk: Use of_property_present()	Rob Herring (Arm)	3	-3/+3
2024-08-02	clk: at91: Use of_property_count_u32_elems() to get property length	Rob Herring (Arm)	1	-2/+3
2024-08-02	clk: renesas: Add family-specific clock driver for RZ/V2H(P)	Lad Prabhakar	4	-0/+838
2024-08-02	clk: renesas: r8a779h0: Add PWM clock	Cong Dang	1	-0/+1
2024-07-31	clk: qcom: fold dispcc-sm8650 info dispcc-sm8550	Dmitry Baryshkov	4	-1811/+24
2024-07-31	clk: qcom: dispcc-sm8550: use rcg2_shared_ops for ESC RCGs	Dmitry Baryshkov	1	-2/+2
2024-07-31	clk: qcom: dispcc-sm8650: Update the GDSC flags	Dmitry Baryshkov	1	-2/+2
2024-07-31	clk: qcom: dispcc-sm8550: make struct clk_init_data const	Dmitry Baryshkov	1	-80/+80
2024-07-31	clk: qcom: dispcc-sm8550: use rcg2_ops for mdss_dptx1_aux_clk_src	Dmitry Baryshkov	1	-1/+1
2024-07-31	clk: qcom: dispcc-sm8550: fix several supposed typos	Dmitry Baryshkov	1	-2/+2
2024-07-31	clk: qcom: Add camera clock controller driver for SM8150	Satya Priya Kakitapalli	3	-0/+2169
2024-07-31	clk: qcom: clk-alpha-pll: Add support for Regera PLL ops	Taniya Das	2	-1/+36
2024-07-31	clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL	Satya Priya Kakitapalli	1	-0/+16
2024-07-31	clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled	Satya Priya Kakitapalli	1	-0/+3
2024-07-31	clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API	Satya Priya Kakitapalli	1	-2/+2
2024-07-31	clk: qcom: clk-alpha-pll: Fix the pll post div mask	Satya Priya Kakitapalli	1	-1/+1
2024-07-31	clk: qcom: gcc-sc8180x: Add missing USB MP resets	Bjorn Andersson	1	-0/+4
2024-07-31	clk: thead: fix dependency on clk_ignore_unused	Drew Fustini	1	-1/+1
2024-07-31	clk: samsung: exynos850: Add TMU clock	Sam Protsenko	1	-1/+6
2024-07-30	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	Geert Uytterhoeven	5	-28/+20
2024-07-30	clk: renesas: rcar-gen4: Remove unused fixed PLL clock types	Geert Uytterhoeven	2	-24/+0
2024-07-30	clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type	Geert Uytterhoeven	2	-10/+0
2024-07-30	clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-5/+5
2024-07-30	clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-7/+7
2024-07-30	clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs	Geert Uytterhoeven	1	-6/+6
2024-07-30	clk: renesas: r8a779a0: Use defines for PLL control registers	Geert Uytterhoeven	1	-4/+9
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs	Geert Uytterhoeven	2	-0/+44
2024-07-30	clk: renesas: rcar-gen4: Add support for fixed variable PLLs	Geert Uytterhoeven	2	-10/+26
2024-07-30	clk: renesas: rcar-gen4: Add support for variable fractional PLLs	Geert Uytterhoeven	2	-7/+18
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional multiplication	Geert Uytterhoeven	1	-15/+54
2024-07-30	clk: renesas: rcar-gen4: Use defines for common CPG registers	Geert Uytterhoeven	5	-21/+27
2024-07-30	clk: renesas: rcar-gen4: Use FIELD_GET()	Geert Uytterhoeven	2	-5/+11
2024-07-30	clk: renesas: rcar-gen4: Clarify custom PLL clock support	Geert Uytterhoeven	1	-15/+17
2024-07-30	clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions	Geert Uytterhoeven	1	-4/+0
2024-07-30	clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register functions	Lad Prabhakar	1	-28/+17
2024-07-30	clk: renesas: rzg2l-cpg: Use devres API to register clocks	Lad Prabhakar	1	-6/+20
2024-07-30	clk: renesas: r8a779h0: Initial clock descriptions should be __initconst	Geert Uytterhoeven	1	-3/+3
2024-07-30	clk: renesas: r8a779g0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1