index
:
wireguard-linux
backport-5.4.y
davem/net
davem/net-next
devel
gregkh/stable-5.4.y
jd/bump-compilers
jd/deferred-aip-removal
jd/new-archs
jd/orphan-parallel
jd/rcu-barrier
jd/shorter-socket-lock
jd/unified-crypt-queue
jd/xdp-l3
stable
update-toolchain
WireGuard for the Linux kernel
Jason A. Donenfeld
about
summary
refs
log
tree
commit
diff
stats
homepage
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
core
/
pci.c
(
follow
)
Age
Commit message (
Expand
)
Author
Files
Lines
2025-05-09
cxl/pci: Add comments to cxl_hdm_decode_init()
Robert Richter
1
-9
/
+22
2025-05-09
cxl/pci: Moving code in cxl_hdm_decode_init()
Robert Richter
1
-8
/
+8
2025-05-09
cxl: Remove else after return
Robert Richter
1
-1
/
+2
2025-04-09
cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()
Li Ming
1
-3
/
+9
2025-04-09
cxl/pci: Update Port GPF timeout only when the first EP attaching
Li Ming
1
-6
/
+4
2025-04-09
cxl/core: Fix caching dport GPF DVSEC issue
Li Ming
1
-8
/
+8
2025-03-14
cxl/pci: Introduce cxl_gpf_get_dvsec()
Davidlohr Bueso
1
-10
/
+20
2025-03-14
cxl/pci: Support Global Persistent Flush (GPF)
Davidlohr Bueso
1
-0
/
+87
2025-01-29
Merge tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Linus Torvalds
1
-3
/
+3
2025-01-03
driver core: Constify API device_find_child() and adapt for various usages
Zijun Hu
1
-2
/
+2
2025-01-02
cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()
Alejandro Lucero
1
-3
/
+3
2024-12-02
module: Convert symbol namespace to string literal
Peter Zijlstra
1
-9
/
+9
2024-09-22
cxl: Calculate region bandwidth of targets with shared upstream link
Dave Jiang
1
-0
/
+23
2024-09-09
cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()
Yanfei Xu
1
-10
/
+11
2024-09-09
cxl/pci: Check Mem_info_valid bit for each applicable DVSEC
Yanfei Xu
1
-4
/
+4
2024-09-09
cxl/pci: Remove duplicated implementation of waiting for memory_info_valid
Yanfei Xu
1
-36
/
+5
2024-09-09
cxl/pci: Fix to record only non-zero ranges
Yanfei Xu
1
-7
/
+1
2024-09-03
cxl/pci: Remove duplicate host_bridge->native_aer checking
Li Ming
1
-11
/
+6
2024-09-03
cxl/pci: cxl_dport_map_rch_aer() cleanup
Li Ming
1
-20
/
+13
2024-09-03
cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()
Li Ming
1
-4
/
+9
2024-09-03
cxl/port: Use __free() to drop put_device() for cxl_port
Li Ming
1
-4
/
+2
2024-08-09
cxl/pci: Get AER capability address from RCRB only for RCH dport
Li Ming
1
-4
/
+6
2024-07-17
cxl/core/pci: Move reading of control register to immediately before usage
Foryun Ma
1
-4
/
+4
2024-05-08
cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders
Dave Jiang
1
-0
/
+29
2024-05-08
PCI/CXL: Move CXL Vendor ID to pci_ids.h
Dave Jiang
1
-3
/
+3
2024-03-13
lib/firmware_table: Provide buffer length argument to cdat_table_parse()
Robert Richter
1
-1
/
+7
2024-03-12
cxl/pci: Get rid of pointer arithmetic reading CDAT table
Robert Richter
1
-36
/
+41
2024-03-12
cxl/pci: Rename DOE mailbox handle to doe_mb
Robert Richter
1
-10
/
+10
2024-02-16
cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window
Robert Richter
1
-3
/
+3
2024-01-29
cxl/pci: Skip to handle RAS errors if CXL.mem device is detached
Li Ming
1
-12
/
+31
2023-12-22
cxl: Calculate and store PCI link latency for the downstream ports
Dave Jiang
1
-0
/
+36
2023-12-08
cxl/cdat: Free correct buffer on checksum error
Ira Weiny
1
-7
/
+6
2023-11-02
cxl/pci: Change CXL AER support check to use native AER
Terry Bowman
1
-2
/
+2
2023-10-31
Merge branch 'for-6.7/cxl-qtg' into cxl/next
Dan Williams
1
-12
/
+40
2023-10-27
cxl: Add support for reading CXL switch CDAT table
Dave Jiang
1
-5
/
+17
2023-10-27
cxl: Add checksum verification to CDAT from CXL
Dave Jiang
1
-7
/
+23
2023-10-27
cxl/pci: Disable root port interrupts in RCH mode
Terry Bowman
1
-0
/
+32
2023-10-27
cxl/pci: Add RCH downstream port error logging
Terry Bowman
1
-0
/
+96
2023-10-27
cxl/pci: Map RCH downstream AER registers for logging protocol errors
Terry Bowman
1
-0
/
+36
2023-10-27
cxl/pci: Update CXL error logging to use RAS register address
Terry Bowman
1
-13
/
+31
2023-10-27
cxl/pci: Add RCH downstream port AER register discovery
Robert Richter
1
-0
/
+15
2023-06-25
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
1
-2
/
+2
2023-06-25
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
1
-23
/
+4
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
1
-2
/
+2
2023-05-18
cxl: Wait Memory_Info_Valid before access memory related info
Dave Jiang
1
-9
/
+76
2023-05-18
cxl/port: Enable the HDM decoder capability for switch ports
Dan Williams
1
-4
/
+23
2023-05-13
cxl: Add missing return to cdat read error path
Dave Jiang
1
-0
/
+1
2023-04-22
cxl/port: Fix port to pci device assumptions in read_cdat_data()
Dan Williams
1
-6
/
+7
2023-04-18
cxl/pci: Rightsize CDAT response allocation
Lukas Wunner
1
-17
/
+19
2023-04-18
cxl/pci: Simplify CDAT retrieval error path
Dave Jiang
1
-11
/
+12
[next]