Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-03-17 | fpga: zynq: Add support for encrypted bitstreams | 1 | -3/+25 | |
2017-02-10 | fpga zynq: Use the scatterlist interface | 1 | -39/+135 | |
2017-02-10 | fpga zynq: Check the bitstream for validity | 1 | -0/+21 | |
2017-02-10 | fpga zynq: Check for errors after completing DMA | 1 | -22/+32 | |
2016-11-29 | fpga zynq: Fix incorrect ISR state on bootup | 1 | -7/+10 | |
2016-11-29 | fpga zynq: Remove priv->dev | 1 | -11/+8 | |
2016-11-29 | fpga zynq: Add missing \n to messages | 1 | -11/+11 | |
2016-11-10 | fpga-mgr: add fpga image information struct | 1 | -4/+6 | |
2015-10-23 | fpga: zynq-fpga: Fix issue with drvdata being overwritten. | 1 | -3/+4 | |
2015-10-23 | fpga: zynq-fpga: Change fw format to handle bin instead of bit. | 1 | -22/+2 | |
2015-10-23 | fpga: zynq-fpga: Fix unbalanced clock handling | 1 | -2/+2 | |
2015-10-17 | fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 | 1 | -0/+533 |