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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-09-29drm/amdgpu/gfx10: use common function to init CP fwLikun Gao1-78/+8
2022-09-29drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcodeHawking Zhang1-187/+9
2022-08-30drm/amdgpu: only init tap_delay ucode when it's included in ucode binaryHawking Zhang1-25/+35
2022-08-16drm/amdgpu: reduce reset timeVictor Zhao1-2/+7
2022-08-16Revert "drm/amd/amdgpu: add pipe1 hardware support"Michel Dänzer1-1/+1
2022-07-25drm/amd/amdgpu: add TAP_DELAYS upload support for gfx10Chengming Gui1-1/+52
2022-07-13drm/amdgpu/mes: ring aggregatged doorbell when mes queue is unmappedLe Ma1-11/+71
2022-06-08drm/amdgpu: fix scratch register access method in SRIOVZhenGuo Yin1-3/+4
2022-06-06drm/amd/amdgpu: add pipe1 hardware supportArunpravin Paneer Selvam1-1/+1
2022-06-06drm/amd/amdgpu: Enable high priority gfx queueArunpravin Paneer Selvam1-7/+25
2022-05-26drm/amdgpu/gfx: fix typos in commentsJulia Lawall1-1/+1
2022-05-26drm/amdgpu/gfx10: rework KIQ programmingHaohui Mai1-14/+13
2022-05-26drm/amdgpu: Set CP_HQD_PQ_CONTROL.RPTR_BLOCK_SIZE correctlyHaohui Mai1-1/+1
2022-05-26drm/amdgpu: Clean up of initializing doorbells for gfx_v9 and gfx_v10Haohui Mai1-17/+0
2022-05-18drm/amdgpu: Unmap legacy queue when MES is enabledLuben Tuikov1-1/+1
2022-05-06drm/amdgpu: nuke dynamic gfx scratch reg allocationChristian König1-23/+4
2022-05-05drm/amdgpu: simplify the return expressionMinghao Chi1-11/+2
2022-05-05drm/amdgpu/gfx10: Avoid uninitialised variable 'index'Mike Lothian1-1/+2
2022-05-04drm/amdgpu/gfx10: enable kiq to map mes ringJack Xiao1-1/+15
2022-05-04drm/amdgpu: add mes unmap legacy queue routineJack Xiao1-0/+6
2022-05-04drm/amdgpu: enable mes kiq N-1 test on sienna cichlidJack Xiao1-12/+20
2022-05-04drm/amdgpu/gfx10: add mes support for gfx ib testJack Xiao1-13/+33
2022-05-04drm/amdgpu/gfx10: add mes queue fence handlingJack Xiao1-20/+40
2022-05-04drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2Jack Xiao1-7/+20
2022-05-04drm/amdgpu/gfx10: inherit vmid from mqdJack Xiao1-0/+8
2022-05-04drm/amdgpu/gfx10: associate mes queue id with fence v2Jack Xiao1-1/+2
2022-05-04drm/amdgpu/gfx10: use per ctx CSA for de metadataJack Xiao1-11/+28
2022-05-04drm/amdgpu/gfx10: use per ctx CSA for ce metadataJack Xiao1-9/+19
2022-05-04drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2Jack Xiao1-55/+56
2022-05-04drm/amdgpu: use ring structure to access rptr/wptr v2Jack Xiao1-18/+19
2022-04-26drm/amdgpu: Fix out-of-bound access for gfx_v10_0_ring_test_ib()Haohui Mai1-2/+1
2022-04-11drm/amdgpu: Fix incorrect enum typeGrigory Vasilyev1-1/+1
2022-04-08drm/amdgpu: expand cg_flags from u32 to u64Evan Quan1-1/+1
2022-03-31drm/amdgpu: fix incorrect GCR_GENERAL_CNTL addressRuili Ji1-3/+3
2022-03-25drm/amdgpu/gfx10: enable gfx1037 clock counter retrieval functionPrike Liang1-0/+1
2022-03-15drm/amdgpu: only allow secure submission on rings which support thatLang Yu1-0/+1
2022-03-02drm/amdgpu/gfx10: drop unused cyan skillfish firmwareAlex Deucher1-11/+1
2022-03-02drm/amdgpu: enable gfxoff routine for GC 10.3.7Prike Liang1-0/+3
2022-03-02drm/amdgpu: enable gfx power gating for GC 10.3.7Prike Liang1-0/+2
2022-03-02drm/amdgpu: enable gfx clock gating control for GC 10.3.7Prike Liang1-0/+1
2022-02-17drm/amdgpu: add gc 10.3.6 supportYifan Zhang1-3/+84
2022-02-16drm/amdgpu/gfx10: Add GC 10.3.7 SupportPrike Liang1-1/+52
2022-02-16drm/amdgpu: make cyan skillfish support code more consistentAlex Deucher1-3/+1
2022-02-11drm/amdgpu: add support for GC 10.1.4Lang Yu1-0/+9
2022-02-09drm/amdgpu: fix gmc init fail in sriov modeYang Wang1-1/+3
2022-01-25drm/amdgpu: retire rlc callbacks sriov_rreg/wregHawking Zhang1-114/+0
2022-01-25drm/amdgpu: init rlcg_reg_access_ctrl for gfx10Hawking Zhang1-4/+34
2022-01-25drm/amdgpu: switch to get_rlcg_reg_access_flag for gfx10Hawking Zhang1-39/+2
2021-11-24drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as wellAlex Deucher1-2/+13
2021-11-05drm/amdgpu: correctly toggle gfx on/off around RLC_SPM_* register accessEvan Quan1-0/+5
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