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path: root/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c (follow)
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2023-10-09drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang1-1/+1
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-09-20drm/amdgpu: Use function for IP version checkLijo Lazar1-1/+1
Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Clean up style problems in mmhub_v2_3.cSrinivasan Shanmugam1-12/+13
Fixes the following: ERROR: code indent should use tabs where possible WARNING: Missing a blank line after declarations WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: suspect code indent for conditional statements (8, 24) + if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | [...] + *flags |= AMD_CG_SUPPORT_MC_MGCG; Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)Hawking Zhang1-5/+5
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-03drm/amdgpu: rename vram_scratch into mem_scratchChristian König1-1/+1
Rename vram_scratch into mem_scratch and allow allocating it into GTT as well. The only problem with that is that we won't have a default page for the system aperture any more. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-12-06drm/amdgpu: fix mmhub register base coding errorYang Wang1-1/+1
fix MMHUB register base coding error. Fixes: ec6837591f992 ("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-05-04drm/amdgpu: save the setting of VM_CONTEXT_CNTLJack Xiao1-0/+2
MES firmware needs the setting of VM_CONTEXT_CNTL to perform vmid switch. Save the initial setting when hub initializing. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-04-08drm/amdgpu: expand cg_flags from u32 to u64Evan Quan1-1/+1
With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: add support for gmc10 for gc 10.3.6Yifan Zhang1-0/+1
this patch adds support for gmc10. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-14drm/amdgpu: don't override default ECO_BITs settingHawking Zhang1-1/+0
Leave this bit as hardware default setting Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-10-04drm/amdgpu: convert IP version array to include instancesAlex Deucher1-1/+1
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amdgpu/mmhub2.1: convert to IP version checkingAlex Deucher1-3/+3
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: add mmhub client support for yellow carpAlex Deucher1-0/+1
To help debugging GPUVM page faults. Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: Delete two unneeded bool conversionsZhen Lei1-2/+2
The result of an expression consisting of a single relational operator is already of the bool type and does not need to be evaluated explicitly. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-15drm/amdgpu: Calling address translation functions to simplify codesOak Zeng1-2/+1
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: split mmhub callbacks into ras and non-ras onesHawking Zhang1-1/+0
mmhub ras is only avaiable in cerntain mmhub ip generation. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amdgpu: Fix masking binary not operator on two mask operationsColin Ian King1-2/+2
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d6e7520 ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu1-23/+61
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amdgpu: switched to cached noretry setting for vangoghHawking Zhang1-1/+1
global noretry setting is cached to gmc.noretry Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-08drm/amdgpu: use AMDGPU_NUM_VMID when possibleNirmoy Das1-1/+1
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-01drm/amdgpu: enable AGP aperture on gmc10.x (v2)Alex Deucher1-4/+4
Just a small optimization for accessing system pages directly. Was missed for gmc v10 since the feature landed for older gmcs while we were still on the emulator or gmc10 and we use the AGP aperture for zfb on the emulator. v2: fix up the system aperture as well Reviewed-and-tested-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu/mmhub2.3: print client id string for mmhubAlex Deucher1-6/+43
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: add mmhub v2.3 for vangogh (v4)Huang Rui1-0/+552
There are too many register offset mismatch between mmhub v2.0 and v2.3. E.X: mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32: 0x072b(v2.0) 0x0940(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32: 0x072c(v2.0) 0x0941(v2.3) mmMMVM_INVALIDATE_ENG0_REQ: 0x06e3(v2.0) 0x0a01(v2.3) mmMMVM_INVALIDATE_ENG0_ACK: 0x06f5(v2.0) 0x0a02(v2.3) mmMMVM_CONTEXT0_CNTL: 0x06c0(v2.0) 0x0740(v2.3) mmMMVM_L2_PROTECTION_FAULT_STATUS: 0x068c(v2.0) 0x070c(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmDAGB0_CNTL_MISC2: 0x0071(v2.0) 0x0096(v2.3) ... Continuing using the same file mmhub v2.0 is not good choice, it will introduce a lot of checking with ASIC types. And also easy to introduce the issues that offset not align, this kind of issues are really hard to find. Van Gogh's mmhub vm invalidation is actually caused by the offset mismatch as well. So it would like to create a new file rather than stick to re-use orignal mmhub v2.0 here. v2: add missed translate_further programming. v3: sync with latest code v4: add missing callbacks Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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