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WireGuard for the Linux kernel
Jason A. Donenfeld
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path:
root
/
drivers
/
gpu
/
drm
/
amd
/
amdgpu
/
soc15_common.h
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Age
Commit message (
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Author
Files
Lines
2021-06-07
drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
Peng Ju Zhou
1
-2
/
+2
2021-06-04
drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
shaoyunl
1
-2
/
+2
2021-05-21
drm/amdgpu: Indirect register access for Navi12 sriov
Peng Ju Zhou
1
-36
/
+51
2021-04-09
drm/amdgpu: indirect register access for nv12 sriov
Peng Ju Zhou
1
-42
/
+33
2021-03-23
drm/amdgpu: enable watchdog feature for SQ of aldebaran
Dennis Li
1
-0
/
+30
2021-03-23
drm/amdgpu: add ras support for gfx of aldebaran
Dennis Li
1
-0
/
+18
2020-07-01
drm/amdgpu: fix unused variable
James Zhu
1
-6
/
+9
2020-04-24
drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used later
Monk Liu
1
-0
/
+3
2020-03-16
drm/amdgpu: revise RLCG access path
Monk Liu
1
-3
/
+2
2019-11-26
drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG
Nathan Chancellor
1
-0
/
+1
2019-08-02
drm/amdgpu: cleanup vega10 SRIOV code path
Monk Liu
1
-2
/
+3
2019-05-24
drm/amdgpu: move the VCN DPG mode read and write to VCN
Leo Liu
1
-21
/
+0
2019-05-24
drm/amdgpu: add basic func for RLC program reg
Trigger Huang
1
-1
/
+56
2018-12-18
drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG
James Zhu
1
-2
/
+7
2018-09-26
drm/amdgpu/soc15: fix warnings in register macro
Alex Deucher
1
-1
/
+1
2018-09-26
drm/amdgpu:Add DPG mode read/write macro
James Zhu
1
-0
/
+20
2018-09-13
drm/amdgpu:Add error message when register failed to reach expected value
James Zhu
1
-0
/
+2
2018-05-24
drm/amdgpu: Add SOC15_WAIT_ON_RREG macro define
Rex Zhu
1
-0
/
+15
2017-12-13
drm/amdgpu: convert nbio to use callbacks (v2)
Alex Deucher
1
-16
/
+0
2017-12-08
drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset
Shaoyun Liu
1
-5
/
+1
2017-12-08
drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array
Shaoyun Liu
1
-6
/
+0
2017-12-08
drm/amdgpu: Use dynamic IP offset for register access on SOC15
Shaoyun Liu
1
-26
/
+8
2017-07-14
drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define
Shaoyun Liu
1
-0
/
+7
2017-06-15
drm/amd/amdgpu: Add offset variant to SOC15 macros
Tom St Denis
1
-0
/
+14
2017-04-28
drm/amd/amdgpu: Introduce new read/write macros for SOC15
Tom St Denis
1
-1
/
+19
2017-03-29
drm/amdgpu: add common soc15 headers
Ken Wang
1
-0
/
+57