| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2026-05-27 | drm/amd/display: Delete max_clks_by_state from DCE clock manager (v2) | 1 | -17/+0 | |
| 2026-05-27 | drm/amd/display: Remove min/max clock levels from clk_mgr (v2) | 1 | -15/+0 | |
| 2026-05-27 | drm/amd/display: Delete unimplemented dm_pp_apply_power_level_change_request() (v2) | 1 | -9/+0 | |
| 2023-06-09 | drm/amd/display: Clean FPGA code in dc | 1 | -12/+8 | |
| 2020-10-27 | drm/amd/display: correct asic type check V2 | 1 | -2/+5 | |
| 2020-10-05 | drm/amd/display: Avoid set zero in the requested clk | 1 | -2/+1 | |
| 2019-12-05 | drm/amd/display: rename core_dc to dc | 1 | -6/+6 | |
| 2019-10-25 | drm/amd/display: move dispclk vco freq to clk mgr base | 1 | -2/+2 | |
| 2019-07-18 | drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct | 1 | -2/+2 | |
| 2019-05-31 | drm/amd/display: move clk_mgr files to right place | 2 | -0/+278 |
