aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/gpu/drm/amd/display/dc/dce
AgeCommit message (Expand)AuthorFilesLines
2017-09-26drm/amd/display: DMCU PSR RefactorAmy Zhang4-314/+354
2017-09-26drm/amd/display: HDMI deep color mode audio issueCharlene Liu3-22/+14
2017-09-26drm/amd/display: fix incorrect programming for YCbCr422 and YCbCr420Charlene Liu1-3/+9
2017-09-26drm/amd/display: fix 12bpc truncate to 10bpcCharlene Liu1-9/+9
2017-09-26drm/amd/display: audio bug fix part 1: Add missing audio ACRCharlene Liu4-30/+63
2017-09-26drm/amd/display: Don't attempt to program missing register fields on DCE8Jordan Lazare2-13/+28
2017-09-26drm/amd/display: Fix logic that causes segfault on DP display.Zeyu Fan1-10/+12
2017-09-26drm/amd/display: Fix program pix clk logic to unblock deep color set.Zeyu Fan1-5/+5
2017-09-26drm/amd/display: fix psr status waitDmytro Laktyushkin2-13/+25
2017-09-26drm/amd/display: HDMI YCbCr422 12bpc pixel format issueCharlene Liu3-27/+50
2017-09-26drm/amd/display: Fix 64-bit divisionHarry Wentland1-1/+1
2017-09-26drm/amd/display: remove CV-specific timing standardCharlene Liu1-4/+0
2017-09-26drm/amd/display: Support ABM without PPlibAnthony Koo2-24/+9
2017-09-26drm/amd/display: Move backlight from encoder to ABMAnthony Koo4-303/+280
2017-09-26drm/amd/display: DMCU Compile and LoadAnthony Koo6-38/+593
2017-09-26drm/amd/display: Proper de-allocation of OPPJoshua Aberback2-39/+6
2017-09-26drm/amd/display: Add missing MI masksLeon Elazar1-0/+2
2017-09-26drm/amd/display: Fix missing conditions in hw sequencer.Zeyu Fan1-1/+1
2017-09-26drm/amd/display: rename BGRA8888 to ABGR8888Tony Cheng1-2/+2
2017-09-26drm/amd/display: refactor clk_resync to avoid assertionTony Cheng1-27/+30
2017-09-26drm/amd/display: remove SIGNAL_TYPE_WIRELESSTony Cheng1-1/+0
2017-09-26drm/amd/display: remove hw_crtc_timingTony Cheng1-1/+1
2017-09-26drm/amd/display: No audio output heard from DP panelHersen Wu1-2/+2
2017-09-26drm/amd/display: Fixing some fallout from dc_target removalLeon Elazar1-0/+7
2017-09-26drm/amd/display: Pass visible flag into surface programmingYongqiang Sun2-2/+4
2017-09-26drm/amd/display: drop min/max wrappersDave Airlie1-2/+2
2017-09-26drm/amd/display: Don't fail validation for SIGNAL_TYPE_VIRTUALYongqiang Sun1-0/+3
2017-09-26drm/amd/display: remove HDMI deep color debug flagTony Cheng1-3/+0
2017-09-26drm/amd/display: fix Infoframe byte 28-31 doesn't get written out to registerTony Cheng1-2/+2
2017-09-26drm/amd/display: Check hdr support before setting.Yongqiang Sun1-11/+16
2017-09-26drm/amd/display: Fix warnings in DCHarry Wentland1-6/+0
2017-09-26drm/amd/display: Fix misleading indentation bug in link_encoderHarry Wentland1-1/+2
2017-09-26drm/amd/display: Fix DP PHY test pre-emphasis not set properlyHersen Wu1-1/+1
2017-09-26drm/amd/display: limit HBR3 support to Polaris and upTony Cheng2-26/+6
2017-09-26drm/amd/display: simplify link_encoderTony Cheng1-60/+4
2017-09-26drm/amd/display: set HBR3 and TPS4 capable flagsHersen Wu1-0/+10
2017-09-26drm/amd/display: Add missing function to fix crash for DP Test pattern 4Hersen Wu1-0/+3
2017-09-26drm/amd/display: debug opt disable hdmi deep colorTony Cheng1-0/+3
2017-09-26drm/amd/display: DAL3: HDR10 Infoframe encodingAndrew Wong1-5/+15
2017-09-26drm/amd/display: Allow multiple instance of DTO regsTony Cheng1-3/+7
2017-09-26drm/amd/display: Implement gamma correction using input LUTAric Cyr2-6/+0
2017-09-26drm/amd/display: minor clock source refactorDmytro Laktyushkin2-37/+40
2017-09-26drm/amd/display: Fix Regamma end pointAnthony Koo1-2/+2
2017-09-26drm/amd/display: OPP refactor and consolidation for DCE.Zeyu Fan3-1/+1415
2017-09-26drm/amd/display: fix hotplug regression after code refactorRoman Li1-1/+1
2017-09-26drm/amd/display: Add debug option to disable dmcuYongqiang Sun1-0/+3
2017-09-26drm/amd/display: Resolved HDMI assert in dalYongqiang Sun1-3/+3
2017-09-26drm/amd/display: Moved swizzle parameter translation to dc.Yongqiang Sun1-10/+1
2017-09-26drm/amd/display: Fix HDMI scaling corruption issue.Zeyu Fan2-1/+12
2017-09-26drm/amd/display: Change locking of registers when flipping frames.Andrew Wong1-8/+3
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.