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path: root/drivers/gpu/drm/amd/display/dc/dsc/dcn20
AgeCommit message (Expand)AuthorFilesLines
2026-05-11drm/amd/display: Fix warningsClay King1-4/+4
2026-05-05drm/amd/display: Fix type mismatches using guards and explicit castsGaghik Khachatrian1-1/+2
2026-04-17drm/amd/display: Fix narrowing boundaries and eDP parser assignmentGaghik Khachatrian1-2/+2
2026-04-17drm/amd/display: Fix implicit narrowing conversion warningsGaghik Khachatrian1-6/+6
2026-04-17drm/amd/display: Rework YCbCr422 DSC policyRelja Vojvodic1-1/+1
2026-03-30Revert "drm/amd/display: Rework YCbCr422 DSC policy"Relja Vojvodic1-1/+1
2026-03-23drm/amd/display: Rework YCbCr422 DSC policyRelja Vojvodic1-1/+1
2025-10-28drm/amd/display: Add more DC HW state info to underflow loggingKaren Chen2-0/+9
2025-10-13drm/amd/display: Correct slice width calculation for YCbCr420Relja Vojvodic1-1/+1
2025-09-15drm/amd/display: Add DSC padding for OVT SupportRelja Vojvodic1-1/+2
2025-05-05drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.Bhuvanachandra Pinninti2-7/+6
2024-06-27drm/amd/display: Adjust reg field for DSC wait for disconnectRyan Seto1-1/+3
2024-06-27drm/amd/display: Reset DSC memory statusDuncan Ma2-17/+16
2024-05-08drm/amd/display: reset DSC clock in post unlock updateWenjing Liu2-8/+13
2024-04-26drm/amd/display: Add some DCN401 reg name to macro definitionsAurabindo Pillai1-0/+11
2023-11-29drm/amd/display: Refactor DSC into component folderBhuvana Chandra Pinninti2-0/+1369
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