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2020-10-14drm/amd/display: Fix module load hangs when connected to an eDPRodrigo Siqueira1-5/+5
It was recently introduced a change that enables driver to disable streams if pixel clock changes. Consequently, the code path executed in the disable vbios function expanded to an encoder verification part. The encoder loop is nested inside the pipe count loop, and both loops share the 'i' variable in control of their flow. This situation may lead to an infinite loop because the encoder loop constantly updates the `i` variable, making the first loop always positive. As a result, we can see a soft hang during the module load (modprobe amdgpu) and a series of dmesg log that looks like this: kernel:[ 124.538727] watchdog: BUG: soft lockup - CPU#2 stuck for 22s! [modprobe:1000] RSP: 0018:ffffabbf419bf0e8 EFLAGS: 00000282 RAX: ffffffffc0809de0 RBX: ffff93b35ccc0000 RCX: ffff93b366c21800 RDX: 0000000000000000 RSI: 0000000000000141 RDI: ffff93b35ccc0000 RBP: ffffabbf419bf108 R08: ffffabbf419bf164 R09: 0000000000000001 R10: 0000000000000003 R11: 0000000000000003 R12: 0000000008677d40 R13: 0000000000000141 R14: ffff93b35cfc0000 R15: ffff93b35abc0000 FS: 00007f1400717540(0000) GS:ffff93b37f680000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005649b66b0968 CR3: 00000003e0fec000 CR4: 0000000000350ee0 Call Trace: amdgpu_device_rreg+0x17/0x20 [amdgpu] amdgpu_cgs_read_register+0x14/0x20 [amdgpu] dm_read_reg_func+0x3a/0xb0 [amdgpu] get_pixel_clk_frequency_100hz+0x30/0x50 [amdgpu] dc_commit_state+0x8f1/0xae0 [amdgpu] ? drm_calc_timestamping_constants+0x101/0x160 [drm] amdgpu_dm_atomic_commit_tail+0x39d/0x21a0 [amdgpu] ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu] ? kfree+0xc3/0x390 ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu] ... RSP: 002b:00007fff26009bd8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 RAX: ffffffffffffffda RBX: 000055a8025bea50 RCX: 00007f140085c89d RDX: 0000000000000000 RSI: 000055a8025b8290 RDI: 000000000000000c RBP: 0000000000040000 R08: 0000000000000000 R09: 0000000000000000 R10: 000000000000000c R11: 0000000000000246 R12: 000055a8025b8290 R13: 0000000000000000 R14: 000055a8025bead0 R15: 000055a8025bea50 This issue was fixed by introducing a second variable for the internal loop. Fixes: 8353d30e747f4e ("drm/amd/display: disable stream if pixel clock changed with link active") Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-09drm/amd/display: Fix OPTC_DATA_FORMAT programmingDmytro Laktyushkin3-16/+11
This should be programmed with timing rather than with odm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-09drm/amd/display: Don't allow pstate if no support in blankAlvin Lee1-1/+1
[Why] We will hang if we report switch in VACTIVE but not in VBLANK and DPG_EN = 1 [How] Block switch in ACTIVE if not supported in BLANK Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: HDMI remote sink need mode validation for LinuxFangzhi Zuo1-1/+1
[Why] Currently mode validation is bypassed if remote sink exists. That leads to mode set issue when a BW bottle neck exists in the link path, e.g., a DP-to-HDMI converter that only supports HDMI 1.4. Any invalid mode passed to Linux user space will cause the modeset failure due to limitation of Linux user space implementation. [How] Mode validation is skipped only if in edid override. For real remote sink, clock limit check should be done for HDMI remote sink. Have HDMI related remote sink going through mode validation to elimiate modes which pixel clock exceeds BW limitation. Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Change to correct unit on audio rateChris Park1-3/+2
[Why] Formula uses kHz in their formula while our driver operates with Hz. [How] Divide audio rate by 1000 on the initial variable that is entered into formula. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Avoid set zero in the requested clkRodrigo Siqueira1-2/+1
[Why] Sometimes CRTCs can be disabled due to display unplugging or temporarily transition in the userspace; in these circumstances, DCE tries to set the minimum clock threshold. When we have this situation, the function bw_calcs is invoked with number_of_displays set to zero, making DCE set dispclk_khz and sclk_khz to zero. For these reasons, we have seen some ATOM bios errors that look like: [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for more than 5secs aborting [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck executing EA8A (len 761, WS 0, PS 0) @ 0xEABA [How] This error happens due to an attempt to optimize the bandwidth using the sclk, and the dispclk clock set to zero. Technically we handle this in the function dce112_set_clock, but we are not considering the case that this value is set to zero. This commit fixes this issue by ensuring that we never set a minimum value below the minimum clock threshold. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-30drm/amd/display: add pipe reassignment prevention code to dcn3Dmytro Laktyushkin1-12/+49
Add code to gracefuly handle any pipe reassignment occuring on dcn3 hardware. This should only happen when new surfaces are used for an update rather than old ones updated. Fixes: 69fc1f4b976cea ("amd/drm/display: avoid dcn3 on flip opp change for slave pipes") Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: remove duplicate call to rn_vbios_smu_get_smu_version()Dirk Gouders1-1/+0
Commit 78fe9f63947a2b ("drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions") added a call to rn_vbios_smu_get_smu_version() to set clk_mgr->smu_ver. That field is initialized prior to the if-statement, already. Fixes: 78fe9f63947a2b (drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions) Signed-off-by: Dirk Gouders <dirk@gouders.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Sung Lee <sung.lee@amd.com> Cc: Yongqiang Sun <yongqiang.sun@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: make two symbols staticJason Yan1-2/+2
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2740:6: warning: symbol 'dce110_set_cursor_position' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2785:6: warning: symbol 'dce110_set_cursor_attribute' was not declared. Should it be static? Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: make get_color_space_type() staticJason Yan1-1/+1
This addresses the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c:180:26: warning: symbol 'get_color_space_type' was not declared. Should it be static? Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29amd/drm/display: avoid dcn3 on flip opp change for slave pipesDmytro Laktyushkin1-3/+40
At the moment on flip opp reassignment does not work in all cases for non root pipes. This change simply makes sure we prefer pipes not used previously when splitting in dcn3. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Eric Bernstein <eric.bernstein@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: disable stream if pixel clock changed with link activeChiawen Huang1-1/+0
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Revert check for flip pending before locking pipesAric Cyr4-14/+13
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Add debug param to force dio disableWesley Chalmers2-0/+4
[WHY] At the moment, some tests are failing because cur_link_settings is invalid. As a workaround, add an option to force dio disable. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Calc DLG from dummy p-state if full p-state unsupportedJoshua Aberback3-41/+80
[Why] Currently, when full p-state changes are not supported, DLG parameters are calculated for no p-state support at all. However, we are required to always support dummy p-state changes, so we should instead calculate DLG based on dummy p-state latency when full p-state is unsupported. This behaviour already exists for DCN2. [How] - move DLG calculation inside WM calculation - if p-state unsupported, do not recalculate for set A, instead copy from set C, and perform DLG calculation with dummy p-state latency Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: disable stream if pixel clock changed with link activeChiawen Huang2-4/+60
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Ensure all debug bits are passed to fwWyatt Wood1-2/+3
[Why] Some debug bits are not being copied from driver to fw. [How] Copy debug bits properly. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoderEric Bernstein2-10/+18
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Update NV1x SR latency valuesAlvin Lee1-2/+2
[Why] HW team measurement requires updating values [How] Update bounding box values Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-25drm/amdgpu/display: fix CFLAGS setup for DCN30Alex Deucher1-2/+16
Properly handle clang and older versions of gcc. Fixes: e77165bf7b02a3 ("drm/amd/display: Add DCN3 blocks to Makefile") Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: optimize code runtime a bitBernard Zhao1-9/+1
In the function dal_ddc_service_query_ddc_data, get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. This change is to make the code run a bit fast. Signed-off-by: Bernard Zhao <bernard@vivo.com> Changes since V1: *get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. Link for V1: *https://lore.kernel.org/patchwork/patch/1309014/ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: [FIX] update clock under two conditionsLewis Huang1-2/+4
[Why] Update clock only when non-seamless boot stream exists creates regression on multiple scenerios. [How] Update clock in two conditions 1. Non-seamless boot stream exist. 2. Stream_count = 0 Fixes: 598c13b21e25 ("drm/amd/display: update clock when non-seamless boot stream exist") Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <Qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org>
2020-09-22drm/amd/display: 3.2.104Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: TMDS Fallback transitionChris Park1-0/+2
[Why] HDMI requires fallback to TMDS by redetection in order to switch PHY settings. This avoids black out when link training fail during mode setting, link quality update, disable driver sequence. [How] Allow driver to redetect HDMI displays based on retraining or fallback mechanism. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Check for flip pending before locking pipes.Taimur Hassan4-13/+14
[Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Implement PSR wait for enable/disableWyatt Wood3-3/+28
[Why] For DMUB implementation of PSR, the 'wait' parameter, used to determine if driver should wait for PSR enable/disable, is not implemented correctly. [How] Implement wait for PSR enable/disable. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: allow DP RX to use more cr aux rd interval delayWenjing Liu1-1/+18
[why] Regression is caused by previous change with attempt to correct the extended cr aux rd interval delay due to mis interpretation of the DP specs. The change turns out not working well with certain RXs. So we decided to keep the cr aux rd interval logic as before. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Enable DP YCbCr420 mode support for DCN10Gary Li1-1/+1
[WHY] In DCN10 when a panel with YCbCr420 capability is connected via USB-C to HDMI active dongle, no YCbCr420 option is listed in Radeon settings. [HOW] Enable DP YCbCr420 mode support for DCN10 Signed-off-by: Gary Li <gary.li@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Increase timeout for DP DisableWesley Chalmers1-2/+2
[WHY] When disabling DP video, the current REG_WAIT timeout of 50ms is too low for certain cases with very high VSYNC intervals. [HOW] Increase the timeout to 102ms, so that refresh rates as low as 10Hz can be handled properly. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org>
2020-09-22drm/amd/display: Fix ODM policy implementationWesley Chalmers1-5/+6
[WHY] Only the leftmost ODM pipe should be offset when scaling. A previous code change was intended to implement this policy, but a section of code was overlooked. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org>
2020-09-22drm/amd/display: eDP intermittent black screen during PnPPeikang Zhang6-0/+7
[Why] We dont's turn off backlight before power off eDP (VDD), which is a violation of eDP specs. [How] Power off eDP backlight before power off eDP Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Bug in dce_is_panel_backlight_on()Peikang Zhang2-3/+11
[Why] dce_is_panel_backlight_on() will return wrong value if LVTMA_BLON_OVRD is 0 [How] When LVTMA_BLON_OVRD is 0, read LVTMA_PWRSEQ_TARGET_STATE instead Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: 3.2.103Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Fix incorrect backlight register offset for DCNDavid Galiffi1-1/+1
[Why] Typo in backlight refactor introduced wrong register offset. [How] SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2). Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org>
2020-09-17drm/amd/display: Delete duplicated argument to '&&' or '||'Ye Bin2-4/+4
Fixes coccicheck warnig: drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:282:12-42: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:3240:12-42: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5520:7-91: duplicated argument to && or || drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5309:86-122: duplicated argument to && or || Fixes: 6725a88f88a7 ("drm/amd/display: Add DCN3 DML") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ye Bin <yebin10@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-17drm/amd/display: dc/clk_mgr: make function staticMauro Rossi1-1/+1
[Why] linux-next kernel test robot reported the following problem: warning: no previous prototype for 'dce60_get_dp_ref_freq_khz' [-Wmissing-prototypes] [How] mark dce60_get_dp_ref_freq_khz() as static Fixes: 3ecb3b794e2c "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)" Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-17drm/amd/display: Add missing "Copy GSL groups when committing a new context"Bhawanpreet Lakha1-0/+11
[Why] "Copy GSL groups when committing a new context" patch was accidentally removed during a refactor Patch: 21ffcc94d5b ("drm/amd/display: Copy GSL groups when committing a new context") [How] Re add it Fixes: b6e881c9474 ("drm/amd/display: update navi to use new surface programming behaviour") Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: optimize code runtime a bitBernard Zhao1-9/+5
In fnction is_cr_done & is_ch_eq_done, when done = false happened once, no need to circle left ln_count. This change is to make the code run a bit fast. Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm: amd/display: fix spelling of "function"Randy Dunlap8-8/+8
Fix spellos of "function" in drivers/gpu/drm/amd/display/. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: Remove duplicate includeChen Zhou1-1/+0
Remove duplicate header which is included twice. Signed-off-by: Chen Zhou <chenzhou10@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: update clock when non-seamless boot stream existLewis Huang1-2/+2
[Why] Seamless boot skip porgram clock when set path mode. It cause driverprogram clock after unblank stream. [How] update clock when non-seamless boot stream exist Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: update dcn30_optc header with missing declarationsDmytro Laktyushkin2-3/+6
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: get socBB from VBIOSJun Lei3-1/+90
[why] Some SOC BB paramters may vary per SKU, and it does not make sense for driver to hardcode these values [how] Parse the values from VBIOS if available, and use them if valid Signed-off-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: Further fix of psr eDP p-state warningFangzhi Zuo1-1/+1
[Why] psr doesn't get fully disabled before hitting hubbub1_wm_change_req_wa. [How] Pass TRUE to "wait" parameter to get psr fully disabled. Follow-Up fix to: dc: PSR eDP p-state warning occurs intermittently after unplug DP Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: update nv1x stutter latenciesJun Lei1-2/+2
[why] Recent characterization shows increased stutter latencies on some SKUs, leading to underflow. [how] Update SOC params to account for this worst case latency. Signed-off-by: Jun Lei <jun.lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: fix compile warning in dmlRoman Li1-1/+1
[Why] gcc version 5.4.0 fails compilation with: ‘PixelPTEReqHeightPTEs’ may be used uninitialized in this function [-Werror=maybe-uninitialized] [How] Initialized variable explicitly with 0 Signed-off-by: Roman Li <roman.li@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: remove dc context from transfer functionJosip Pavic5-17/+1
[Why] The ctx field of dc_transfer_func is not always populated and therefore isn't reliable. [How] Remove dc context from dc_transfer_func Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: Update idle optimization handlingJoshua Aberback3-6/+14
[How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: implement notify stream maskEric Yang4-0/+37
[Why] Send stream active state info to DMUB [How] Implement GPINT to notify stream mask Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: 3.2.102Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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