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2026-08-12drm/amd/display: fix BT.2020 YCbCr output CSC matrices for DCENathan Lucas2-6/+8
The commit cited by the Fixes tag added separate limited and full-range BT.2020 YCbCr entries to the DCE output CSC tables, but populated both entries with the same matrix copied from the common DC table. That matrix combined full-range scaling with limited-range luma offset and was incorrect for both limited and full-range output. Replace the coefficients in both entries in the DCE paths with those from the new COLOR_SPACE_YCBCR2020_LIMITED_TYPE and COLOR_SPACE_YCBCR2020_FULL_TYPE entries in the preceding commit ("drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix"). Fixes: 51e6668ab4ba ("drm/amd/display: add missing CSC entries for BT.2020 for DCE IPs") Assisted-by: OpenAI-Codex:GPT-5.6-Sol Tested-by: Igor Paunovic <royalnet026@gmail.com> Tested-by: Satyajit Roy <sroy14@alum.utk.edu> Signed-off-by: Nathan Lucas <nlucasgit@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amd/display: fix BT.2020 YCbCr limited output CSC matrixNathan Lucas1-11/+20
COLOR_SPACE_YCBCR2020_TYPE, which is selected for COLOR_SPACE_2020_YCBCR_LIMITED color_space, has coefficients that are incorrect for limited-range output. Its luma and chroma scaling is full-range so output is too bright and colors are incorrect. COLOR_SPACE_YCBCR2020_TYPE is closer to a full-range conversion matrix with incorrect luma offset, so correct the luma offset for full-range and rename it to COLOR_SPACE_YCBCR2020_FULL_TYPE. Add COLOR_SPACE_YCBCR2020_LIMITED_TYPE with correct scaling and range for limited-range output. Fix related functions so COLOR_SPACE_YCBCR2020_LIMITED_TYPE and COLOR_SPACE_YCBCR2020_FULL_TYPE are correctly selected based on dc_color_space. Derivation of both matrices follows ITU-T H.273: Table 4, MatrixCoefficients 9, BT.2020-NCL weights: KR = 0.2627, KB = 0.0593, KG = 1 - KR - KB = 0.6780. Equations 45-47 in matrix form: [ KR KG KB 0 ] M2020_NCL = [ -KR/(2(1-KB)) -KG/(2(1-KB)) 1/2 0 ] [ 1/2 -KG/(2(1-KR)) -KB/(2(1-KR)) 0 ] [ 0 0 0 1 ] Limited and Full transforms based on equations 30-32 and 36-38 with bit depth 10, normalized by 1023: [ 876/1023 0 0 64/1023 ] MLimited = [ 0 896/1023 0 512/1023 ] [ 0 0 896/1023 512/1023 ] [ 0 0 0 1 ] [ 1023/1023 0 0 0 ] MFull = [ 0 1023/1023 0 512/1023 ] [ 0 0 1023/1023 512/1023 ] [ 0 0 0 1 ] M2020_NCL_Limited = MLimited x M2020_NCL M2020_NCL_Full = MFull x M2020_NCL The upper three rows of M2020_NCL_* are stored in CR, Y, CB order. Each M2020_NCL_* value is stored as Round(value * 8192) in its 16-bit two's-complement representation. Fixes: 973a9c810c78 ("drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix") Assisted-by: OpenAI-Codex:GPT-5.6-Sol Tested-by: Igor Paunovic <royalnet026@gmail.com> Tested-by: Satyajit Roy <sroy14@alum.utk.edu> Signed-off-by: Nathan Lucas <nlucasgit@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amd/display: Relax frame size limit for dcn5/6 DML core funcs filesIvan Lipski1-0/+8
[Why] During compilation with allmodconfig with KASAN, there appears a Werror: dml2_core_dcn5_funcs_mode_programming.c:11:13: error: stack frame size (2400) exceeds limit (2048) in 'dcn5_mode_programming' [-Werror,-Wframe-larger-than] The dcn5/dcn6 dml2_core_*_funcs_mode_{programming,support} files were split out of dml2_core_dcn4_calcs.o, which carries a relaxed -Wframe-larger-than limit via $(frame_warn_flag) (2056 normally, or 4096 for clang + KASAN/KCSAN + COMPILE_TEST). The split-out files were never added to the per-file CFLAGS override list, so they inherited the strict global default of 2048. This is why these files trip the frame size warning under KASAN while the larger dml2_core_dcn4_calcs.o does not. [How] Apply the same $(frame_warn_flag) and CFLAGS_REMOVE handling used for dml2_core_dcn4_calcs.o to the split-out files: - dml2_core_dcn5_funcs_mode_programming.o - dml2_core_dcn5_funcs_mode_support.o - dml2_core_dcn6_funcs_mode_programming.o - dml2_core_dcn6_funcs_mode_support.o Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6") Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Reported-by: Mark Brown <broonie@kernel.org> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Fix crash in hwss_set_output_transfer_func()Timur Kristóf1-1/+2
The pipe_ctx->plane_res.hubp pointer is NULL on all DCE hardware, which causes a kernel NULL pointer dereference on all Vega and older GPUs. Let's add a simple NULL check. Fixes: 6bfca938471b ("drm/amd/display: Refactor DPP_SET_OUTPUT_TRANSFER_FUNC to drop pipe_ctx") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Cc: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Check for tg ops in dce110_set_avmuteRay Wu1-1/+4
Some older DCE timing generators do not implement is_tg_enabled in their ops table. Calling it unconditionally when waiting for AV mute frames causes a NULL pointer dereference on Southern Islands dGPUs when turning the display off over HDMI. Check that tg and the required ops exist before waiting for frames. Fixes: 414da24137ac ("drm/amd/display: Add AV mute wait frames to dce110_set_avmute") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5557 Tested-by: Viktor Jägersküpper <viktor_jaegerskuepper@freenet.de> Signed-off-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Promote DC to 3.2.392Taimur Hassan1-1/+1
This version brings along the following updates: - Add KUnit tests for crtc functions. - Add KUnit tests for crtc functions. - Add support for dynamic FFE levels. - Configure all CRC engines in pipe CRC source path. - Enable DCN6 compilation. - Fix ABM over VABC. - Fix CRC engine 1 enable/disable on DCN3.1.2+. - Fix MCM blend LUT issues. - Fix seamless mode switch not triggering for HDR to SDR transition. - Fix wb_info leak and NULL deref in writeback. - Increase fclk change latency on dcn351. - Refactor stream validation. - Resize MST HDCP per-connector arrays to 32. - Unify force_yuv debugfs into force_yuv_pixel_format. - Update VRR info packet to support 12-bit refresh rates. Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Migrate color manager HW and fix MCM blend LUT issuesRafal Ostrowski29-1616/+773
Combine two related color manager improvements: 1. Migrate MCM/RMCM, shaper and 3DLUT HW programming to dc_plane_cm - Continue convergence with upstream Color Manager refactor - Migrate MCM/RMCM, shaper and 3DLUT programming for dcn401+ to dc_plane_cm - Unify MCM programming across both legacy and 3DLUT DMA paths - Add 3DLUT DMA broadcast support for multi-pipe planes 2. Reprogram MCM blend LUT on blend_enable falling edge - Fix issue where SDR desktop remained desaturated after video playback - Detect blend_enable falling edge (1->0) in surface update detection - Force MCM LUT reprogramming on blend state change Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add FFE level defaultsRelja Vojvodic16-0/+16
[How & Why] Follow-up change to set defaults for HDMI FRL training Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: switch max FFE level cap based on FRL link rateRelja Vojvodic1-1/+2
[How & Why] - Add support for dynamic FFE levels based on debug config and link rate Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Update BW bounding box unconditionally for DCN6Alvin Lee1-6/+2
[Description] DCN6 needs to update BW bounding box in hw init in order to propagate the Alt-Ch aperture info into DML. In this case update unconditionally on dcn6 HW init. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Configure all CRC engines in pipe CRC source pathWayne Lin1-1/+2
Iterate every CRC engine instance when enabling or disabling the pipe CRC source so DCN31x OTG_CRC1_EN is handled alongside OTG_CRC_EN, matching the legacy shared enable behavior used by DisplayCRC multi-ROI. Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Fix CRC engine 1 enable/disable on DCN3.1.2+Wayne Lin11-18/+69
[Why] Multi-ROI CRC uses OTG_CRC1_EN for the second engine, but the driver only toggled OTG_CRC_EN and cleared the whole OTG_CRC_CNTL register on disable. [How] Program engine 1 via OTG_CRC1_EN where supported, disable each engine independently by crc_eng_inst, and add the missing mask on relevant DCN ASICs. Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add missing OTG_CRC1_SELECT mask for DCN3.2Wayne Lin1-0/+1
[Why] Configuring CRC engine 1 via optc35_configure_crc() triggers ASSERT(mask != 0) in dc_helper.c when programming OTG_CRC1_SELECT. The DCN3.2 OPTC mask list inherited from dcn32 is missing this field, so ROI[1] CRC cannot be enabled in DisplayCRC mode on DCN3.5/3.51. [How] Add OTG_CRC1_SELECT to OPTC_COMMON_MASK_SH_LIST_DCN3_2, matching the existing dcn10 definition so REG_UPDATE can program CRC engine 1. Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add missing DCN42B register definesMatthew Stewart2-49/+17
[why] These registers are used, but were missing from their corresponding lists. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Increase fclk change latency on dcn351Sung-huai Wang1-2/+2
[Why] fclk change latency is longer than expected on dcn351. [How] Increate fclk change latency from 24us to 32us. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Sung-huai Wang <Danny.Wang@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Fix seamless mode switch not triggering for HDR to SDR transitionKarthi Kandasamy5-16/+46
[Why] The seamless mode switch was not getting triggered during HDR to SDR transitions, and no DPCD write was observed. Root cause analysis revealed that incorrect panel capabilities were being reported for PSR SU panels. Due to the wrong capabilities, the OS was not invoking the seamless mode switch API, resulting in no DPCD communication and also gated eDP teardown across the seamless mode switch hold. [How] Fixed by setting the correct power panel capabilities for PSR SU panels. This ensures the OS receives accurate panel capability information and triggers the seamless mode switch API as expected, restoring proper DPCD writes during HDR to SDR transitions. The DC commit sequence was tearing the eDP down anyway -- backlight off, ABM disable, DPMS off, PSR/Replay enable state cleared, PHY TX off, OTG/OPTC off; all these actions are blocked now with the skip_implict_edp_power_control Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Ensure dtbclk is enabledCharlene Liu5-6/+46
[why] ensure dtbclk is enabled before hdmistreamclk_en pmfw could stop dtbclk on idle. driver needs to ensure dtbclk enabled is enabled before hdmistreamclk_en also disable debounce timer on dcn42. Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Enable DCN6 sources compilationAurabindo Pillai108-43/+2795
- Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add new sources for DCN6Aurabindo Pillai105-1/+47847
Add DCN6 code to DC, DML2, and DMUB Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: use proper context for loggingJiri Slaby (SUSE)1-11/+9
The same as the rest of the code, get_ss_info_from_atombios() uses calc_pll_cs->ctx->logger for logging. But calc_pll_cs->ctx is initialized only later in calc_pll_max_vco_construct(). Therefore, any output using DC_LOG_SYNC() leads to a NULL pointer deference in get_ss_info_from_atombios(). According to Sashiko, the very same problem exists in dce112_get_pix_clk_dividers() and dcn3_get_pix_clk_dividers() too. To avoid accessing the NULL context, use clk_src->base.ctx->logger everywhere. That context in base is initialized earlier in dce110_clk_src_construct() and dce112_clk_src_construct(). Before get_ss_info_from_atombios() or Sashiko's get_pix_clk_dividers functions above are actually called. This is done by redefining DC_LOGGER to CTX->logger. Before: dce110_clk_src_construct() did: -> sets clk_src->base.ctx = ctx; -> ss_info_from_atombios_create() -> get_ss_info_from_atombios() <- uses calc_pll_cs->ctx # BOOM -> calc_pll_max_vco_construct() <- sets calc_pll_cs->ctx After: dce110_clk_src_construct() does: -> sets clk_src->base.ctx = ctx; -> ss_info_from_atombios_create() -> get_ss_info_from_atombios() <- uses clk_src->base.ctx Closes: https://bugzilla.suse.com/show_bug.cgi?id=1271175 Closes: https://lore.kernel.org/all/a9ee54e6-2413-4156-9bde-d528ae3c63a3@kernel.org/ Fixes: 1296423bf23c ("drm/amd/display: define DC_LOGGER for logger") Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Cc: Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Rodrigo Siqueira <siqueira@igalia.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix DML file discovery for out-of-tree buildsPrike Liang1-2/+5
By anchoring the search to the DML top-level Makefile directory, FPU CFLAGS are now correctly applied to all relevant source files. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Silence link_dpms I2C retimer failuresAlan Swanson1-8/+8
Commit a4f01bf729b2 ("drm/amd/display: Refactor and fix link_dpms I2C") had also changed the "Set retimer failed" messages from DC_LOG_DEBUG() to DC_LOG_ERROR(). This unfortunately can create log spam. Change those back to DC_LOG_DEBUG() only. Fixes: a4f01bf729b2 ("drm/amd/display: Refactor and fix link_dpms I2C") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5520 Signed-off-by: Alan Swanson <reiver@improbability.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Promote DC to 3.2.391Santhosh, Ashwin1-1/+1
This DC patchset brings improvements in multiple areas. In summary, we have: * Expand KUnit test * dm refactor ongoing * Fix apple 5k tiled monitor light up * Fix frl dsc upstream mistake * dcn42 fixes Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Santhosh, Ashwin <Ashwin.Santhosh@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: dispatch compressed FRL cap check inside dml1_frl_cap_chk_interFangzhi Zuo1-5/+5
[why] DSC over HDMI FRL (e.g. 4k144) was pruned by DML mode support because the compressed FRL cap check was never reached. dml32_TruncToValidBPP() validates the FRL output by calling dml1_frl_cap_chk_inter() directly. The compressed-vs-uncompressed dispatch (if params->compressed -> dml1_frl_cap_chk_compressed()) had been moved up into the top-level dml1_frl_cap_chk() wrapper, leaving dml1_frl_cap_chk_inter() as uncompressed-only. As a result a DSC stream routed through TruncToValidBPP was validated against the full uncompressed bandwidth, failed the cap check, and the mode was pruned (vlevel == num_states). [how] Move the compressed dispatch back into dml1_frl_cap_chk_inter() so every caller of _inter() (including TruncToValidBPP) honours params->compressed. This matches the internal DAL tree. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: plumb PMO per-plane pstate methods into mode_supportAlexander Chechik3-11/+17
[Why] mode_support reads mode_lib.ms.uclk_pstate_switch_modes to enforce the vactive pstate margin, but nothing populates it: the memset clears it and the PMO selection is never passed in. The check always sees na and never runs, so a plane with negative vactive margin can still pass and blank the display. [How] Add a const per-plane pstate-method pointer to mode_support_ex, point it at stage3.pstate_switch_modes when stage 3 has run (NULL otherwise), and copy it into mode_lib.ms after the memset. Scope the support-required check to the vactive methods it governs (vactive, fw_vactive_drr) so SVP, DRR and vblank planes are not rejected by the vactive support flag. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alexander Chechik <alexander.chechik@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix rounding errors in CalculatePrefetchScheduleMatthew Stewart1-3/+6
[why] Rounding errors were causing mode validation to fail in some cases when it should not. (IE. Increasing fclk from a lower value could lead to validation failure, which should not happen.) Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fixes for dcn42b_soc_bb.hMatthew Stewart1-2/+2
[why] Some values were found to be incorrect. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: add DalForceMaxDisplayClock debug option to DML2Justin Chen1-0/+5
[Why & How] need to apply the debug option check for max displayclk. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Justin Chen <Justin.Chen5@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: enforce UCLK pstate support in mode_supportAlexander Chechik3-22/+36
[Why] mode_support does not require UCLK pstate today, so later PMO optimization stages can push a plane's VActive latency-hiding margin below zero without rechecking that the config still supports UCLK pstate. This can blank the display on high-bandwidth configs. [How] Plumb the PMO-selected per-plane pstate method into mode_support and fail the config only when UCLK pstate is required (method != na) but not supported. For planes committed to a vactive method, require a non-negative VActive latency-hiding margin, and skip the check when all streams are blanked. No-op the PMO DCN42 pstate test (returning false only on the initial candidate so the optimize/FAMS2 stage-3 setup still runs), since reserved time is guaranteed by the override and the vactive margin is now enforced in core mode_support. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alexander Chechik <alexander.chechik@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: change dcc_rate from 1 to 2 for log use onlyCharlene Liu1-4/+4
[why] The dcc_rate value does not affect any watermark, TTU or DLG output; it only affects the Z8 stutter-related logging. The hardware DisplayModeSupported formula uses a dcc_rate of 4, while DML2 currently uses 1. [how] Change dcc_rate from 1 to 2 so the logged value is closer to the hardware formula. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: check if dml21_add_phantom_plane() is successfulAlex Deucher1-8/+7
Verify that the phantom plane was allocated to avoid a later segfault. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4970 Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources") Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix divide-by-zero in calculate_mcache_setting on zero viewportGeorge Zhang1-6/+25
If a plane reaches calculate_mcache_setting with a zero-area viewport, calculate_mcache_setting exits early with num_mcaches == 0 and mvmpg_width/height == 0. This will cause a divide-by-zero panic and can also cause an underflow on num_mcaches. Fix this by changing calculate_mcache_setting to bool and adding guards after each calculate_mcache_row_bytes call. If num_mcaches or mvmpg_width/height is zero, return a false. Callers will propagate the failure as a rejected mode, which prevents the panic. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5302 Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add get replay residency functionHuang, Leon2-0/+15
[Why&How] Add dc interface to export link service function for getting Replay residency Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Huang, Leon <Leon.Huang1@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: adjust floating point format for gamut remap when neededClay King27-70/+186
[Why] The MPCCs different gamut remap matrices allow for S2D13 and S3D12 floating point formats, but only S2D13 is used. There may be cases where more integer bits are required. [How] Switch to S3D12 if any entries in the remap matrix cannot fit in S2D13. Otherwise, prefer the extra precision of S2D13. Communicate the max value that hw can support to dm via dc color caps. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Correct vblank_end calc for fams cmd packetNicholas Carbones1-1/+1
[Why] By changing how we populate vblank_nom, constraining vblank size, the vblank_end calculation for the fams command packet gets affected. We add up v_active with a new vblank_nom value for stream pstate's nom_vtotal, which describes the vtotal and nominal refresh rate, and that causes underflow. [How] Set nom_vtotal equal to the timing's v_total. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Use current mpc pipe in set output transfer funcTomasz Siemek1-2/+2
[why] Only the top pipe had the output transfer function programmed. [how] Program the current pipe from the MPC chain during fast sequence build. Reviewed-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add AV mute wait frames to dce110_set_avmuteRay Wu1-1/+20
Port the three-frame wait logic from dcn30_set_avmute to dce110_set_avmute so that older DCN versions (1.0, 2.0) also wait for GCP packets to be sent out before proceeding. This ensures HDMI sinks properly process the mute state, preventing garbled display after link re-establishment. Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5167 Reviewed-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix force FRL rate debug settingRelja Vojvodic2-2/+4
[Why & How] - force FRL rate debug bit was not correctly forcing requested FRL rate Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Port DCN4+ MCIF ARB programming to new formatDillon Varone9-29/+227
[WHY&HOW] DML2.1 now outputs MCIF arbiter programming, but using a new structure. Change DCN401 and DCN42 to use this new format. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Promote DC to 3.2.390Taimur Hassan1-1/+1
This DC patchset brings improvements in multiple areas. In summary, we have: * Unified dc_update_state commit interface with dc_probe model, dc_state_get_status, and perfmon BLS sequence * DCN42 enhancements including mcache programming, PMFW DF C-state client, and DCCG clocking fix * DML2.1 writeback validation plus MCIF ARB and watermark/latency updates * Color management refactor to dc_plane_cm with plane/CRTC colorop test coverage * Greatly enhanced KUnit coverage across amdgpu_dm, connector, CRC, DMUB, and color management * HDMI AV mute timing, DP link training logging, and Apple Studio Display fixes * Code cleanup including DCE trim from DCN-only builds and HWSS refactors Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add SPL UPSP upsampling and YUV422 scaling supportWayne Lin2-26/+234
- Add YUV422/YUV444 pixel format definitions - Handle YUV422 chroma scaling ratios - Use separate horizontal and vertical viewport divisors - Add UPSP upsampling register programming - Refine tap selection for horizontally and vertically subsampled formats Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add DCHUBBUB_HW_DEBUG offset/maskMatthew Stewart1-1/+6
Add missing register defines for DCN42B. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Reduce DML reinitialization when params don't changeClara Wong1-1/+16
[WHY] Reinitializing DML causes an extra ~8s delay in gaming mode preset switches on some systems [HOW] Don't reinitialize DML unless params/caps have changed Reviewed-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Clara Wong <Clara.Wong@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: hide Apple Studio Display secondary tileJerry Zuo1-0/+1
The Apple Studio Display exposes a 2x1 tiled panel over two SST DP links. The primary tile advertises the full 5120x2880 mode (with DSC on the bandwidth-sufficient link) while the secondary carries a per-tile 2560x2880 timing on a link without sufficient bandwidth. Report the non-primary tile connector as disconnected during detect so compositors only see the primary DP link and configure a single 5K mode instead of driving both tiled streams independently. Drive the behaviour from an EDID quirk: add a disable_second_tile panel patch that apply_edid_quirks() sets for the affected Apple Studio Display panel IDs (0xAE3A, 0xAE42, 0xAE46), and have detect() hide the secondary tile when the sink carries that quirk. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42Leo Chen8-1/+91
[Why] DCN must not gate DF C-state locally via the DCHUBBUB ALLOW_SELF_REFRESH controls: forcing a local "disallow" during MM-stutter re-entry can wedge the fabric and hang boot. When DCN is disallowing c-state or has invalid watermarks we should be explicit about it rather than using the watermark force selector. [How] Register DCN as a client of PMFW's DF C-state arbiter and signal over DALSMC whether DCN permits DF C-state; PMFW allows DF C-state only once every client (including DCN) has voted "allow". - dc_clocks.cstate_allow: last DCN vote acked by PMFW - clk_mgr_funcs::notify_cstate_disable(clk_mgr, disable) prepare_bandwidth and headless dc_power_down_on_boot vote Allow; hardware_release votes Disallow; init_clocks (D0 entry) only clears the cache (cstate_allow) so the next allow re-syncs with PMFW. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Make dc_state_update const in commit pathWenjing Liu2-23/+23
[Why] The state-update commit path only reads the caller's update descriptor, it never mutates the dc_state_update root. Making the pointer const documents that contract. [How] Add const to the updates parameter of dc_update_state and dc_check_state_update. Mark the single-assignment locals in dc_update_state_init const and replace the memset plus field-by-field assignment with a compound literal initializer. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Wire probe commit path into dc_update_stateWenjing Liu11-179/+427
[Why] The dc_update_state commit interface and the dc_probe object model existed but were not connected: there was no path to validate, commit, and program a probe through the update pipeline, nor to read the result back. The measurement waits on OTG frame edges and must not block fast updates. [How] - Move the per-commit scratch off dc_stream_state onto a dc-owned pool; acquire at init, release on cleanup or prepare failure, serialized by the DM global lock every commit path already holds. - dc_update_state drives stream commits, probe-only commits, or both through one staged init/prepare/execute/cleanup loop with a null-arg guard. prepare releases the scratch slot on failure; cleanup releases it on success. - Probe prepare installs the absolute probe set in place; execute calls the perfmon programming hook in the unlocked window and latches results. - Add resource_validate_probe_set, a context-free achievability check shared by dc_validate_global_state (full update) and probe prepare (probe-only). - dc_state_get_status gains a probe status class with a probe filter and a by-type mapping; dc_validation_set gains probes/probe_count. Drop the dead actual_* fields from struct dc_qos_info. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce program_perfmon hwss hook and BLS perfmon sequenceWenjing Liu6-23/+562
[Why] The hubbub perfmon peak-bandwidth path used a monolithic function combining counter configuration and enable in one call, and wrote results into a caller-supplied struct outside the dc_state model. A BLS-driven approach builds the measurement from stateless primitives, gates it to OTG frame boundaries, and stores results in dc_state. [How] - Rename the peak-BW vtable members from "unbounded_bandwidth" to "out_of_order_bandwidth" and split them into arm and start operations. - Add the full set of perfmon BLS primitives - param structs, union members, enum entries, executors, and hwss_add_* builders - for reset, arm, every start_measuring_* and every get_* operation. - Add dc_probe_status (valid, type, result union) plus probe_status[] to dc_state. - Replace the measure_memory_qos hook with program_perfmon(dc, context), which writes results into probe_status[]. - dc_get_qos_info no longer calls the removed hook. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce dc_state_get_status unified status accessorWenjing Liu3-13/+93
[Why] dc_state_get_stream_status() is typed against streams only, leaving no extensible slot for future status classes. The public status accessor signature needs to stay stable as new status classes are added. [How] Add a dc_get_status_type bitmask and the dc_get_status_options / dc_state_status structs. Implement dc_state_get_status() to populate the output object per the options bitmask, and make dc_state_get_stream_status() a shim over it. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Refactor dc_validation_set array into single root structWenjing Liu6-52/+52
[Why] dc_validate_with_context() took a C array of per-stream elements plus a separate count. This flat array cannot be extended to carry global objects without widening the signature further. [How] Rename the per-stream element to dc_validation_stream, and make dc_validation_set a root struct holding streams[MAX_STREAMS] and stream_count. Update dc_validate_with_context() to take a single const dc_validation_set * and propagate the new shape through all DC-layer callers and helpers. Remove the never-implemented dce112_validate_with_context declaration and the orphaned dce100 forward-declare. No behavior change. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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