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path: root/drivers/gpu/drm/amd/include/asic_reg/vcn (follow)
AgeCommit message (Expand)AuthorFilesLines
2024-02-12drm/amdgpu: Add vcn v5_0_0 ip headers (v5)Hawking Zhang2-0/+9299
2023-08-31drm/amdgpu: add UMSCH 4.0 register headersLang Yu2-0/+1304
2023-08-31drm/amdgpu: add vcn 4_0_5 header filesSaleemkhan Jamadar2-0/+10411
2023-06-09drm/amdgpu: Add vcn/jpeg ras err status registersHawking Zhang2-0/+573
2023-06-09drm/amdgpu: add vcn v4_0_3 ip headersHawking Zhang2-0/+12678
2022-11-23drm/amdgpu: add register definition for VCN RAS initializationTao Zhou2-1/+29
2022-05-04drm/amdgpu: add vcn 4_0_0 header files v7Leo Liu2-0/+9665
2022-03-28drm/amdgpu/vcn: Add vcn and jpeg ver 2.6 ras register definitionMohammad Zafar Ziya2-0/+37
2021-03-10drm/amdgpu: add vcn v2_6_0 ip headers (v3)Hawking Zhang2-0/+5997
2020-09-17drm/amdgpu: add VCN 3.0 AV1 registersAlex Deucher1-0/+34
2020-06-03drm/amdgpu: add VCN3.0 register headers (v2)Leo Liu2-0/+7038
2019-10-25drm/amdgpu: add VCN0 and VCN1 needed headersJane Jian1-0/+12
2019-07-18drm/amdgpu: add VCN2.5 headersLeo Liu2-0/+4588
2019-06-20drm/amdgpu: add VCN 2.0 register headersHawking Zhang2-0/+4823
2019-03-19drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headersTom St Denis2-0/+7
2018-10-12drm/amdgpu/vcn:Add new register offset/mask for VCNJames Zhu2-0/+32
2018-09-26drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu2-0/+33
2018-08-27drm/amdgpu: add system interrupt mask for jrbcBoyuan Zhang1-0/+2
2018-08-27drm/amdgpu: add system interrupt register offset headerBoyuan Zhang1-0/+2
2018-06-15drm/amdgpu: add more jpeg register offset headersBoyuan Zhang1-0/+20
2017-12-06drm/amd/include:cleanup raven1 vcn header files.Feifei Xu2-0/+1684
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