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WireGuard for the Linux kernel
Jason A. Donenfeld
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path:
root
/
drivers
/
gpu
/
drm
/
i915
/
display
/
intel_dpll.c
(
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Age
Commit message (
Expand
)
Author
Files
Lines
2024-04-30
drm/i915/dpio: Extract vlv_dpio_phy_regs.h
Ville Syrjälä
1
-0
/
+1
2024-04-30
drm/i915/dpio: Clean up the vlv/chv PHY register bits
Ville Syrjälä
1
-43
/
+42
2024-04-30
drm/i915/dpio: s/pipe/ch/
Ville Syrjälä
1
-24
/
+25
2024-04-30
drm/i915/dpio: s/port/ch/
Ville Syrjälä
1
-27
/
+27
2024-04-30
drm/i915/dpio: Rename some variables
Ville Syrjälä
1
-49
/
+48
2024-04-30
drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
Ville Syrjälä
1
-36
/
+28
2024-04-30
drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
Ville Syrjälä
1
-9
/
+9
2024-04-30
drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
Ville Syrjälä
1
-1
/
+1
2024-04-30
drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
Ville Syrjälä
1
-4
/
+4
2024-04-17
drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
Ville Syrjälä
1
-1
/
+1
2024-04-17
drm/i915: Carve up struct intel_dpll_hw_state
Ville Syrjälä
1
-15
/
+16
2024-04-17
drm/i915: Add local DPLL 'hw_state' variables
Ville Syrjälä
1
-46
/
+56
2024-04-17
drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
Ville Syrjälä
1
-15
/
+15
2024-04-17
drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
Ville Syrjälä
1
-12
/
+9
2024-04-17
drm/i915: Modernize i9xx_pll_refclk()
Ville Syrjälä
1
-8
/
+7
2024-04-17
drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
Ville Syrjälä
1
-33
/
+13
2024-04-17
drm/i915: Extract {i9xx,i8xx,ilk,vlv,chv}_dpll()
Ville Syrjälä
1
-33
/
+68
2024-04-17
drm/i915: Extract i965_dpll_md()
Ville Syrjälä
1
-9
/
+9
2024-04-17
drm/i915: Extract i9xx_dpll_get_hw_state()
Ville Syrjälä
1
-0
/
+30
2024-04-17
drm/i915: Extract ilk_dpll_compute_fp()
Ville Syrjälä
1
-10
/
+12
2024-04-17
drm/i915: Extract ilk_fb_cb_factor()
Ville Syrjälä
1
-15
/
+17
2023-11-17
drm/i915: convert vlv_dpio_read()/write() from pipe to phy
Jani Nikula
1
-51
/
+55
2023-11-17
drm/i915: move *_crtc_clock_get() to intel_dpll.c
Jani Nikula
1
-2
/
+173
2023-10-29
drm/i915/display: Abstract C10/C20 pll calculation
Lucas De Marchi
1
-6
/
+1
2023-10-12
drm/i915/display: Use correct method to free crtc_state
Suraj Kandpal
1
-1
/
+2
2023-08-24
drm/i915: Fully populate crtc_state->dpll
Ville Syrjälä
1
-2
/
+15
2023-08-24
drm/i915: Don't warn about zero N/P in *_calc_dpll_params()
Ville Syrjälä
1
-17
/
+20
2023-06-07
drm/i915/dpll: drop unused but set variables bestn and bestm1
Jani Nikula
1
-3
/
+1
2023-05-15
drm/i915/display: add i915 parameter to I915_STATE_WARN()
Jani Nikula
1
-1
/
+1
2023-04-28
drm/i915/mtl: C20 port clock calculation
Mika Kahola
1
-0
/
+2
2023-04-14
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Radhakrishna Sripada
1
-1
/
+32
2023-01-18
drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under state
Jani Nikula
1
-1
/
+1
2022-11-11
drm/i915: stop including i915_irq.h from i915_trace.h
Jani Nikula
1
-0
/
+1
2022-11-03
drm/i915/dpio: un-inline the vlv phy/channel mapping functions
Jani Nikula
1
-0
/
+1
2022-09-13
drm/i915: Fix TV encoder clock computation
Ville Syrjälä
1
-2
/
+6
2022-09-08
drm/i915: Feed the DPLL output freq back into crtc_state
Ville Syrjälä
1
-3
/
+57
2022-09-08
drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
Ville Syrjälä
1
-4
/
+2
2022-09-08
drm/i915: Do .crtc_compute_clock() earlier
Ville Syrjälä
1
-3
/
+0
2022-08-31
drm/i915: move vbt to display.vbt
Jani Nikula
1
-7
/
+7
2022-08-29
drm/i915: move dpll_funcs to display.funcs
Jani Nikula
1
-12
/
+12
2022-05-31
drm/i915: Clean up DPLL related debugs
Ville Syrjälä
1
-49
/
+26
2022-05-31
drm/i915: Split shared dpll .get_dplls() into compute and get phases
Ville Syrjälä
1
-2
/
+12
2022-04-25
drm/i915: Add crtc .crtc_get_shared_dpll()
Ville Syrjälä
1
-1
/
+46
2022-04-25
drm/i915: Split out dg2_crtc_compute_clock()
Ville Syrjälä
1
-4
/
+18
2022-04-25
drm/i915: Clear the dpll_hw_state when disabling a pipe
Ville Syrjälä
1
-3
/
+3
2022-04-25
drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
Ville Syrjälä
1
-21
/
+3
2022-04-25
drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
Ville Syrjälä
1
-0
/
+10
2022-04-25
drm/i915: Adjust .crtc_compute_clock() calling convention
Ville Syrjälä
1
-34
/
+49
2022-04-25
drm/i915: Make .get_dplls() return int
Ville Syrjälä
1
-4
/
+8
2022-03-10
drm/i915: Populate bxt/glk DPLL clock limits a bit more
Ville Syrjälä
1
-2
/
+1
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