aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/gpu/drm/i915/display/intel_snps_phy.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-02-27drm/i915/snps: convert intel_snps_phy.[ch] to struct intel_displayJani Nikula1-3/+3
2025-01-23drm/i915/snps_phy: Use HDMI PLL algorithm for DG2Ankit Nautiyal1-1/+0
2024-03-21drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()Jani Nikula1-2/+2
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä1-1/+2
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä1-1/+1
2022-06-17drm/i915/mpllb: move mpllb state check to intel_snps_phy.cJani Nikula1-1/+4
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä1-3/+2
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula1-1/+2
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun1-0/+3
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper1-0/+3
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper1-0/+4
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper1-0/+7
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper1-0/+18
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.