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path: root/drivers/gpu/drm/msm/dsi
AgeCommit message (Expand)AuthorFilesLines
2026-03-25drm/msm/dsi: Add support for RGB101010 pixel formatAlexander Koskovich1-0/+22
2026-03-25drm/msm/dsi: add DSI version >= comparison helperAlexander Koskovich1-2/+10
2026-03-25drm/msm/dsi: rename MSM8998 DSI version from V2_2_0 to V2_0_0Alexander Koskovich2-3/+3
2026-03-25drm/msm/dsi: fix hdisplay calculation for CMD mode panelPengyu Luo1-5/+10
2026-03-25drm/msm/dsi: fix bits_per_pclkPengyu Luo1-1/+1
2026-03-25drm/msm/dsi: add the missing parameter descriptionPengyu Luo1-0/+1
2026-03-25drm/msm: add missing MODULE_DEVICE_ID definitionsDmitry Baryshkov2-0/+2
2026-03-25drm/msm/dsi/phy: rename DSI_PHY_7NM_QUIRK_PRE_V4_1 to DSI_PHY_7NM_QUIRK_V4_0Pengyu Luo1-8/+8
2026-03-06drm/msm/dsi: fix pclk rate calculation for bonded dsiPengyu Luo1-6/+23
2026-03-06drm/msm/dsi/phy: fix hardware revisionPengyu Luo1-11/+11
2026-02-24drm/msm/dsi: fix hdisplay calculation when programming dsi registersPengyu Luo1-6/+8
2026-01-21drm/msm/dsi: Add support for KaanapaliYuanjie Yang2-0/+14
2026-01-21drm/msm/dsi/phy: Add support for KaanapaliYuanjie Yang3-0/+26
2026-01-13drm/msm/dsi_phy_14nm: convert from divider_round_rate() to divider_determine_rate()Brian Masney1-6/+1
2025-10-29drm/msm: dsi: fix PLL init in bonded modeNeil Armstrong2-17/+2
2025-09-09drm/msm/dsi/phy: Fix reading zero as PLL rates when unpreparedKrzysztof Kozlowski2-0/+54
2025-09-02drm/msm/dsi/phy_7nm: Fix missing initial VCO rateKrzysztof Kozlowski1-0/+6
2025-09-02drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfieldsKrzysztof Kozlowski1-5/+11
2025-09-02drm/msm/dsi/phy: Toggle back buffer resync after preparing PLLKrzysztof Kozlowski1-0/+4
2025-08-29drm/msm/dsi_phy_7nm: convert from round_rate() to determine_rate()Brian Masney1-9/+7
2025-08-29drm/msm/dsi_phy_28nm: convert from round_rate() to determine_rate()Brian Masney1-11/+10
2025-08-29drm/msm/dsi_phy_28nm_8960: convert from round_rate() to determine_rate()Brian Masney1-16/+16
2025-08-29drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate()Brian Masney1-17/+17
2025-08-29drm/msm/dsi_phy_10nm: convert from round_rate() to determine_rate()Brian Masney1-9/+7
2025-08-13drm/msm/dsi: Fix 14nm DSI PHY PLL Lock issueLoic Poulain2-42/+18
2025-07-05drm/msm: move KMS driver data to msm_kmsDmitry Baryshkov1-2/+2
2025-07-04drm/msm: Use drm_gpuvm types moreRob Clark1-3/+3
2025-07-04drm/msm: Rename msm_gem_address_space -> msm_gem_vmRob Clark1-7/+7
2025-07-04drm/msm/dsi: Add support for SM8750Krzysztof Kozlowski4-0/+78
2025-07-04drm/msm/dsi/phy: Add support for SM8750Krzysztof Kozlowski3-6/+76
2025-06-09drm/msm/dsi/dsi_phy_10nm: Fix missing initial VCO rateKrzysztof Kozlowski1-0/+7
2025-05-02drm/msm/dsi: add DSI support for SA8775PAyushi Makhija2-0/+19
2025-05-02drm/msm/dsi: add DSI PHY configuration on SA8775PAyushi Makhija3-0/+30
2025-05-02drm/msm/dsi/phy: add configuration for SAR2130PDmitry Baryshkov3-0/+26
2025-04-29drm/msm/dsi: convert to devm_drm_bridge_alloc() APILuca Ceresoli1-5/+4
2025-04-07Merge drm/drm-next into drm-misc-nextThomas Zimmermann8-122/+133
2025-03-20drm/bridge: Add encoder parameter to drm_bridge_funcs.attachMaxime Ripard1-1/+2
2025-02-26drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify savingKrzysztof Kozlowski1-4/+6
2025-02-26drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLLKrzysztof Kozlowski1-5/+3
2025-02-26drm/msm/dsi: Add check for devm_kstrdup()Haoxiang Li1-1/+8
2025-02-26drm/msm/dsi: Allow values of 10 and 12 for bits per componentEugene Lepshy1-3/+15
2025-02-26drm/msm/dsi: Set PHY usescase (and mode) before registering DSI hostMarijn Suijten1-11/+21
2025-02-26drm/msm/dsi: Use existing per-interface slice count in DSC timingMarijn Suijten1-4/+4
2025-02-26drm/msm/dsi: Drop unnecessary -ENOMEM messageKrzysztof Kozlowski1-3/+1
2025-02-26drm/msm/dsi: Minor whitespace and style cleanupKrzysztof Kozlowski1-25/+26
2025-02-26drm/msm/dsi: Simplify with dev_err_probe()Krzysztof Kozlowski1-59/+41
2025-02-26drm/msm/dsi: Drop redundant NULL-ifying of clocks on error pathsKrzysztof Kozlowski1-3/+0
2025-02-26drm/msm/dsi/phy: Program clock inverters in correct registerKrzysztof Kozlowski1-1/+1
2025-02-26drm/msm/dsi/phy: Use the header with clock IDsKrzysztof Kozlowski6-3/+7
2025-02-21Merge tag 'drm-msm-fixes-2025-02-20' of https://gitlab.freedesktop.org/drm/msm into drm-fixesDave Airlie1-17/+36
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