| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-02-20 | drm/msm/dsi: Add skeleton 10nm PHY/PLL code |   Archit Taneja | 1 | -0/+9 |
| 2017-02-06 | drm/msm/dsi: Add PHY/PLL for 8x96 | Archit Taneja | 1 | -0/+11 |
| 2016-03-03 | drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init() |   Luis Henriques | 1 | -2/+2 |
| 2015-12-14 | drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY | Archit Taneja | 1 | -0/+10 |
| 2015-08-15 | drm/msm/dsi: Make each PHY type compilation independent |   Hai Li | 1 | -0/+8 |
| 2015-08-15 | drm/msm/dsi: Save/Restore PLL status across PHY reset | Hai Li | 1 | -0/+1 |
| 2015-06-11 | drm/msm/dsi: Add DSI PLL clock driver support | Hai Li | 1 | -0/+89 |
 |
index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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