wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-12-08	PCI: loongson: Limit MRRS to 256	Jiaxun Yang	1	-5/+41
2023-07-18	PCI: Explicitly include correct DT includes	Rob Herring	1	-1/+1
2023-02-13	PCI: loongson: Add more devices that need MRRS quirk	Huacai Chen	1	-9/+24
2023-02-01	PCI: loongson: Prevent LS7A MRRS increases	Huacai Chen	1	-29/+15
2022-07-21	PCI: loongson: Work around LS7A incorrect Interrupt Pin registers	Jianmin Lv	1	-1/+27
2022-07-14	PCI: loongson: Don't access non-existent devices	Huacai Chen	1	-6/+23
2022-07-14	PCI: loongson: Add ACPI init support	Huacai Chen	1	-19/+75
2022-07-14	PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A	Huacai Chen	1	-19/+46
2022-02-17	PCI: Add defines for normal and subtractive PCI bridges	Pali Rohár	1	-1/+1
2020-10-02	PCI: loongson: Simplify loongson_pci_probe() return expression	Qinglang Miao	1	-6/+1
2020-08-05	Merge branch 'pci/host-probe-refactor'	Bjorn Helgaas	1	-8/+0
2020-08-04	PCI: Move DT resource setup into devm_pci_alloc_host_bridge()	Rob Herring	1	-7/+0
2020-07-23	PCI: Set default bridge parent device	Rob Herring	1	-1/+0
2020-07-20	PCI: loongson: Use DECLARE_PCI_FIXUP_EARLY for bridge_class_quirk()	Tiezhu Yang	1	-3/+3
2020-05-27	PCI: Add Loongson PCI Controller support	Jiaxun Yang	1	-0/+247