wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2025-03-23	PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant	Thippeswamy Havalige	1	-1/+2
2025-03-11	PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller	Thippeswamy Havalige	1	-11/+29
2025-03-11	PCI: xilinx-cpm: Fix IRQ domain leak in error path of probe	Thippeswamy Havalige	1	-4/+6
2024-12-18	PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1	Thippeswamy Havalige	1	-11/+39
2023-10-26	PCI: xilinx-cpm: Move IRQ definitions to a common header	Thippeswamy Havalige	1	-31/+7
2022-11-10	PCI: Remove unnecessary <linux/of_irq.h> includes	Bjorn Helgaas	1	-1/+0
2022-07-22	PCI: xilinx-cpm: Add support for Versal CPM5 Root Port	Bharat Kumar Gogada	1	-2/+58
2022-01-03	PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie	Bjorn Helgaas	1	-22/+22
2021-08-02	PCI: Bulk conversion to generic_handle_domain_irq()	Marc Zyngier	1	-2/+2
2021-01-25	PCI: xilinx-cpm: Fix reference count leak on error path	Pan Bian	1	-0/+1
2020-09-07	PCI: xilinx-cpm: Remove leftover bridge initialization	Lorenzo Pieralisi	1	-4/+0
2020-08-05	Merge branch 'pci/host-probe-refactor'	Bjorn Helgaas	1	-9/+6
2020-08-05	PCI: xilinx-cpm: Add Versal CPM Root Port driver	Bharat Kumar Gogada	1	-0/+614