| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-11-01 | dt-bindings: clock: Add AST2500 RMII RCLK definitions |   Andrew Jeffery | 1 | -0/+2 |
| 2018-07-06 | clk: aspeed: Fix SDCLK name |   Lei YU | 1 | -1/+1 |
| 2018-06-04 | Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next |   Stephen Boyd | 1 | -0/+1 |
| 2018-06-01 | clk: aspeed: Add 24MHz fixed clock | Lei YU | 1 | -0/+1 |
| 2018-05-15 | clk:aspeed: Fix reset bits for PCI/VGA and PECI |   Jae Hyun Yoo | 1 | -1/+1 |
| 2018-05-15 | clk: aspeed: Support second reset register |   Joel Stanley | 1 | -0/+1 |
| 2017-12-21 | dt-bindings: clock: Add ASPEED constants | Joel Stanley | 1 | -0/+52 |
 |
index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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