| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-21 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 |   Thomas Gleixner | 1 | -13/+1 |
| 2018-05-15 | clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC |   Jianguo Sun | 1 | -0/+8 |
| 2018-02-27 | clk: hi3798cv200: add COMBPHY0 clock support | Jianguo Sun | 1 | -0/+1 |
| 2018-02-27 | clk: hi3798cv200: fix define indentation |   Shawn Guo | 1 | -27/+27 |
| 2017-06-21 | clk: hisilicon: add usb2 clocks for hi3798cv200 SoC |   Jiancheng Xue | 1 | -1/+8 |
| 2016-11-11 | clk: hisilicon: add CRG driver for Hi3798CV200 SoC | Jiancheng Xue | 1 | -0/+66 |
 |
index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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