| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 |   Thomas Gleixner | 1 | -9/+1 |
| 2018-03-19 | clk: mediatek: update missing clock data for MT7622 audsys |   Ryder Lee | 1 | -1/+2 |
| 2017-11-02 | clk: mediatek: add clocks dt-bindings required header for MT7622 SoC |   Chen Zhong | 1 | -0/+289 |
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index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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