wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2022-12-03	cxl/acpi: Extract component registers of restricted hosts from RCRB	Robert Richter	1	-0/+19
2022-06-28	tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention	Dan Williams	1	-3/+5
2022-05-19	cxl/port: Reuse 'struct cxl_hdm' context for hdm init	Dan Williams	1	-2/+3
2022-05-19	cxl/pci: Drop @info argument to cxl_hdm_decode_init()	Dan Williams	1	-6/+3
2022-05-19	cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()	Dan Williams	1	-4/+4
2022-05-19	cxl/mem: Consolidate CXL DVSEC Range enumeration in the core	Dan Williams	1	-0/+16
2022-05-19	cxl/pci: Move cxl_await_media_ready() to the core	Dan Williams	1	-0/+15
2022-02-08	cxl/core/port: Remove @host argument for dport + decoder enumeration	Dan Williams	1	-16/+12
2022-02-08	cxl/core/hdm: Add CXL standard decoder enumeration to the core	Dan Williams	1	-0/+50
2022-02-08	cxl/core: Generalize dport enumeration in the core	Dan Williams	1	-26/+19
2021-11-15	cxl/test: Mock acpi_table_parse_cedt()	Dan Williams	1	-21/+9
2021-09-21	tools/testing/cxl: Introduce a mocked-up CXL port hierarchy	Dan Williams	1	-0/+171