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2023-02-07Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams2-1/+353
2023-01-26cxl/test: Simulate event log overflowIra Weiny1-1/+49
2023-01-26cxl/test: Add specific eventsIra Weiny1-0/+73
2023-01-26cxl/test: Add generic mock eventsIra Weiny2-1/+232
2023-01-26tools/testing/cxl: Remove cxl_test module math loading messageAlison Schofield1-3/+1
2023-01-25tools/testing/cxl: require 64-bitLuis Chamberlain1-0/+1
2023-01-05tools/testing/cxl: Prevent cxl_test from confusing production modulesDan Williams8-0/+69
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+2
2022-12-05tools/testing/cxl: Require cache invalidation bypassDan Williams1-0/+2
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-2/+114
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams2-7/+407
2022-12-05tools/testing/cxl: Add an RCH topologyDan Williams2-11/+176
2022-12-03tools/testing/cxl: Add XOR Math support to cxl_testAlison Schofield1-3/+115
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter4-0/+33
2022-12-02tools/testing/cxl: Make mock CEDT parsing more robustDan Williams1-4/+6
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-3/+0
2022-12-01tools/testing/cxl: add mechanism to lock mem device for testingDave Jiang1-4/+44
2022-12-01tools/testing/cxl: Add "passphrase secure erase" opcode supportDave Jiang1-0/+102
2022-12-01tools/testing/cxl: Add "Unlock" security opcode supportDave Jiang1-0/+45
2022-12-01tools/testing/cxl: Add "Freeze Security State" security opcode supportDave Jiang1-0/+20
2022-12-01tools/testing/cxl: Add "Disable" security opcode supportDave Jiang1-0/+74
2022-12-01tools/testing/cxl: Add "Set Passphrase" opcode supportDave Jiang1-0/+88
2022-12-01tools/testing/cxl: Add "Get Security State" opcode supportDave Jiang1-7/+37
2022-11-30cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationDave Jiang1-0/+1
2022-11-14tools/testing/cxl: Add bridge mocking supportDan Williams1-2/+8
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-8/+1
2022-11-04tools/testing/cxl: Add a single-port host-bridge regression configDan Williams1-19/+278
2022-11-04tools/testing/cxl: Fix some error exitsDan Williams1-2/+2
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-0/+46
2022-07-21cxl/region: Add region creation supportBen Widawsky1-0/+1
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-3/+7
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-7/+16
2022-07-10tools/testing/cxl: Fix decoder default stateDan Williams1-1/+0
2022-07-10tools/testing/cxl: Add partition supportDan Williams2-63/+28
2022-07-10tools/testing/cxl: Expand CFMWS windowsDan Williams1-5/+5
2022-07-10tools/testing/cxl: Move cxl_test resources to the top of memoryDan Williams1-1/+2
2022-07-09cxl/mem: Convert partition-info to resourcesDan Williams1-1/+1
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-1/+1
2022-06-28tools/testing/cxl: Fix cxl_hdm_decode_init() calling conventionDan Williams1-3/+5
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams1-2/+3
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams1-6/+3
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams3-16/+5
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams3-10/+17
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams3-7/+16
2022-04-12cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()Dan Williams1-1/+1
2022-02-08tools/testing/cxl: Add a physical_node linkDan Williams1-2/+19
2022-02-08tools/testing/cxl: Enumerate mock decodersDan Williams1-20/+98
2022-02-08tools/testing/cxl: Mock one level of switchesDan Williams1-41/+97
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentDan Williams1-1/+1
2022-02-08tools/testing/cxl: Mock dvsec_ranges()Dan Williams1-0/+10
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