blob: 333e423e8bb6b033f5f45c782ef0095d29983158 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
*
* Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-am654-serdes.h>
#include "k3-pinctrl.h"
&serdes1 {
status = "okay";
};
&pcie1_rc {
num-lanes = <1>;
phys = <&serdes1 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy0";
reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&main_pmx0 {
usb0_pins_default: usb0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
};
&serdes0 {
status = "okay";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
};
&dwc3_0 {
status = "okay";
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
phys = <&serdes0 PHY_TYPE_USB3 0>;
phy-names = "usb3-phy";
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "host";
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
&usb0_phy {
status = "okay";
};
|
