aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/arch/um/include/shared/timer-internal.h
blob: 2d2d13c9b46f96246bd06be19a85a610196cc756 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2012 - 2014 Cisco Systems
 * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
 */

#ifndef __TIMER_INTERNAL_H__
#define __TIMER_INTERNAL_H__

#define TIMER_MULTIPLIER 256
#define TIMER_MIN_DELTA  500

enum time_travel_mode {
	TT_MODE_OFF,
	TT_MODE_BASIC,
	TT_MODE_INFCPU,
};

enum time_travel_timer_mode {
	TT_TMR_DISABLED,
	TT_TMR_ONESHOT,
	TT_TMR_PERIODIC,
};

#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT
extern enum time_travel_mode time_travel_mode;
extern unsigned long long time_travel_time;
extern enum time_travel_timer_mode time_travel_timer_mode;
extern unsigned long long time_travel_timer_expiry;
extern unsigned long long time_travel_timer_interval;

static inline void time_travel_set_time(unsigned long long ns)
{
	time_travel_time = ns;
}

static inline void time_travel_set_timer_mode(enum time_travel_timer_mode mode)
{
	time_travel_timer_mode = mode;
}

static inline void time_travel_set_timer_expiry(unsigned long long expiry)
{
	time_travel_timer_expiry = expiry;
}

static inline void time_travel_set_timer_interval(unsigned long long interval)
{
	time_travel_timer_interval = interval;
}
#else
#define time_travel_mode TT_MODE_OFF
#define time_travel_time 0
#define time_travel_timer_expiry 0
#define time_travel_timer_interval 0

static inline void time_travel_set_time(unsigned long long ns)
{
}

static inline void time_travel_set_timer_mode(enum time_travel_timer_mode mode)
{
}

static inline void time_travel_set_timer_expiry(unsigned long long expiry)
{
}

static inline void time_travel_set_timer_interval(unsigned long long interval)
{
}

#define time_travel_timer_mode TT_TMR_DISABLED
#endif

#endif