blob: dd53d36b34e1c0b7200f220e10045181fe43c8b3 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2018 Intel Corporation. All rights reserved.
*/
#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__
#define __INCLUDE_SOUND_SOF_XTENSA_H__
#include <sound/sof/header.h>
/*
* Architecture specific debug
*/
/* Xtensa Firmware Oops data */
struct sof_ipc_dsp_oops_xtensa {
struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
uint32_t exccause;
uint32_t excvaddr;
uint32_t ps;
uint32_t epc1;
uint32_t epc2;
uint32_t epc3;
uint32_t epc4;
uint32_t epc5;
uint32_t epc6;
uint32_t epc7;
uint32_t eps2;
uint32_t eps3;
uint32_t eps4;
uint32_t eps5;
uint32_t eps6;
uint32_t eps7;
uint32_t depc;
uint32_t intenable;
uint32_t interrupt;
uint32_t sar;
uint32_t debugcause;
uint32_t windowbase;
uint32_t windowstart;
uint32_t excsave1;
uint32_t ar[];
} __packed;
#endif
|
