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[
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "BPU_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
}
]
|
