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[
{
"PublicDescription": "Software increment. Instruction architecturally executed (condition code check pass).",
"EventCode": "0x00",
"EventName": "SW_INCR",
"BriefDescription": "Software increment."
},
{
"PublicDescription": "Instruction architecturally executed. This event counts all retired instructions, including those that fail their condition check.",
"EventCode": "0x08",
"EventName": "INST_RETIRED",
"BriefDescription": "Instruction architecturally executed."
},
{
"EventCode": "0x0A",
"EventName": "EXC_RETURN",
"BriefDescription": "Instruction architecturally executed, condition code check pass, exception return."
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR. This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
"EventCode": "0x0B",
"EventName": "CID_WRITE_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR."
},
{
"EventCode": "0x1B",
"EventName": "INST_SPEC",
"BriefDescription": "Operation speculatively executed"
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, write to TTBR. This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
"EventCode": "0x1C",
"EventName": "TTBR_WRITE_RETIRED",
"BriefDescription": "Instruction architecturally executed, condition code check pass, write to TTBR"
},
{
"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.",
"EventCode": "0x21",
"EventName": "BR_RETIRED",
"BriefDescription": "Instruction architecturally executed, branch."
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.",
"EventCode": "0x22",
"EventName": "BR_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted branch."
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
}
]
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