aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
blob: 67ab19e8cf3adbc86f02007bb0f45c048fe431d3 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
[
   {
	    "EventCode": "0x00",
	    "EventName": "uncore_hisi_l3c.rd_cpipe",
	    "BriefDescription": "Total read accesses",
	    "PublicDescription": "Total read accesses",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x01",
	    "EventName": "uncore_hisi_l3c.wr_cpipe",
	    "BriefDescription": "Total write accesses",
	    "PublicDescription": "Total write accesses",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x02",
	    "EventName": "uncore_hisi_l3c.rd_hit_cpipe",
	    "BriefDescription": "Total read hits",
	    "PublicDescription": "Total read hits",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x03",
	    "EventName": "uncore_hisi_l3c.wr_hit_cpipe",
	    "BriefDescription": "Total write hits",
	    "PublicDescription": "Total write hits",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x04",
	    "EventName": "uncore_hisi_l3c.victim_num",
	    "BriefDescription": "l3c precharge commands",
	    "PublicDescription": "l3c precharge commands",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x20",
	    "EventName": "uncore_hisi_l3c.rd_spipe",
	    "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
	    "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x21",
	    "EventName": "uncore_hisi_l3c.wr_spipe",
	    "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
	    "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x22",
	    "EventName": "uncore_hisi_l3c.rd_hit_spipe",
	    "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
	    "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x23",
	    "EventName": "uncore_hisi_l3c.wr_hit_spipe",
	    "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
	    "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x29",
	    "EventName": "uncore_hisi_l3c.back_invalid",
	    "BriefDescription": "Count of the number of L3C back invalid operations",
	    "PublicDescription": "Count of the number of L3C back invalid operations",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x40",
	    "EventName": "uncore_hisi_l3c.retry_cpu",
	    "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
	    "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x41",
	    "EventName": "uncore_hisi_l3c.retry_ring",
	    "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
	    "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
	    "Unit": "hisi_sccl,l3c"
   },
   {
	    "EventCode": "0x42",
	    "EventName": "uncore_hisi_l3c.prefetch_drop",
	    "BriefDescription": "Count of the number of prefetch drops from this L3C",
	    "PublicDescription": "Count of the number of prefetch drops from this L3C",
	    "Unit": "hisi_sccl,l3c"
   }
]