Add support for the RK3399's VOP clocks to rkclock(4).

The main VOP DCLK clocks either have a normal divisor as a parent
or some fractional one.  The clock referred in the device tree to
set the frequency on is the mux itself, which has no divisor.  To
To be able to set the frequency, we need to allow setting it on the
parent anyway.  Thus move the divisor mask check to a later point,
so even though we have no divisor, we can still tell the parent to
adjust itself.

ok kettenis@

2 files changed, 68 insertions, 2 deletions

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 7db66c6343d..6eba4e86009 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rkclock.c,v 1.49 2020/01/22 07:52:37 deraadt Exp $	*/
+/*	$OpenBSD: rkclock.c,v 1.50 2020/02/10 12:41:34 patrick Exp $	*/
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -400,7 +400,7 @@ rkclock_set_frequency(struct rkclock_softc *sc, uint32_t idx, uint32_t freq)
 	int sel_shift, div_shift, i;
 
 	clk = rkclock_lookup(sc, idx);
-	if (clk == NULL || clk->div_mask == 0) {
+	if (clk == NULL) {
 		printf("%s: 0x%08x\n", __func__, idx);
 		return -1;
 	}
@@ -420,6 +420,13 @@ rkclock_set_frequency(struct rkclock_softc *sc, uint32_t idx, uint32_t freq)
 	if (clk->flags & SET_PARENT) {
 		idx = clk->parents[mux];
 		sc->sc_cd.cd_set_frequency(sc, &idx, freq);
+		if (clk->div_mask == 0)
+			return 0;
+	}
+
+	if (clk->div_mask == 0) {
+		printf("%s: 0x%08x\n", __func__, idx);
+		return -1;
 	}
 
 	/*
@@ -1585,6 +1592,28 @@ struct rkclock rk3399_clocks[] = {
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL, RK3399_PLL_NPLL }
 	},
 	{
+		RK3399_DCLK_VOP0, RK3399_CRU_CLKSEL_CON(49),
+		SEL(11, 11), 0,
+		{ RK3399_DCLK_VOP0_DIV, RK3399_DCLK_VOP0_FRAC },
+		SET_PARENT
+	},
+	{
+		RK3399_DCLK_VOP1, RK3399_CRU_CLKSEL_CON(50),
+		SEL(11, 11), 0,
+		{ RK3399_DCLK_VOP1_DIV, RK3399_DCLK_VOP1_FRAC },
+		SET_PARENT
+	},
+	{
+		RK3399_DCLK_VOP0_DIV, RK3399_CRU_CLKSEL_CON(49),
+		SEL(9, 8), DIV(7, 0),
+		{ RK3399_PLL_VPLL, RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
+		RK3399_DCLK_VOP1_DIV, RK3399_CRU_CLKSEL_CON(50),
+		SEL(9, 8), DIV(7, 0),
+		{ RK3399_PLL_VPLL, RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
 		RK3399_ACLK_PERIPH, RK3399_CRU_CLKSEL_CON(14),
 		SEL(7, 7), DIV(4, 0),
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
@@ -1606,6 +1635,18 @@ struct rkclock rk3399_clocks[] = {
 		  RK3399_PLL_VPLL }
 	},
 	{
+		RK3399_ACLK_VOP0, RK3399_CRU_CLKSEL_CON(47),
+		SEL(7, 6), DIV(4, 0),
+		{ RK3399_PLL_VPLL, RK3399_PLL_CPLL, RK3399_PLL_GPLL,
+		  RK3399_PLL_NPLL }
+	},
+	{
+		RK3399_ACLK_VOP1, RK3399_CRU_CLKSEL_CON(48),
+		SEL(7, 6), DIV(4, 0),
+		{ RK3399_PLL_VPLL, RK3399_PLL_CPLL, RK3399_PLL_GPLL,
+		  RK3399_PLL_NPLL }
+	},
+	{
 		RK3399_ACLK_HDCP, RK3399_CRU_CLKSEL_CON(42),
 		SEL(15, 14), DIV(12, 8),
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL, /* RK3399_PLL_PPLL */ }
@@ -1656,6 +1697,16 @@ struct rkclock rk3399_clocks[] = {
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
 	},
 	{
+		RK3399_HCLK_VOP0, RK3399_CRU_CLKSEL_CON(47),
+		0, DIV(12, 8),
+		{ RK3399_ACLK_VOP0 }
+	},
+	{
+		RK3399_HCLK_VOP1, RK3399_CRU_CLKSEL_CON(48),
+		0, DIV(12, 8),
+		{ RK3399_ACLK_VOP1 }
+	},
+	{
 		/* Sentinel */
 	}
 };
diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 061d3c926bf..7c249cb2ebe 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -135,10 +135,21 @@
 #define RK3399_CLK_SDMMC_DRV		154
 #define RK3399_CLK_SDMMC_SAMPLE		155
 
+#define RK3399_DCLK_VOP0		180
+#define RK3399_DCLK_VOP1		181
+#define RK3399_DCLK_VOP0_DIV		182
+#define RK3399_DCLK_VOP1_DIV		183
+#define RK3399_DCLK_VOP0_FRAC		185
+#define RK3399_DCLK_VOP1_FRAC		186
+
 #define RK3399_ACLK_PERIPH		192
 #define RK3399_ACLK_PERILP0		194
 #define RK3399_ACLK_CCI			201
 #define RK3399_ACLK_GMAC		213
+#define RK3399_ACLK_VOP0_NOC		216
+#define RK3399_ACLK_VOP0		217
+#define RK3399_ACLK_VOP1_NOC		218
+#define RK3399_ACLK_VOP1		219
 #define RK3399_ACLK_HDCP		222
 #define RK3399_ACLK_VIO			227
 #define RK3399_ACLK_EMMC		240
@@ -168,6 +179,10 @@
 #define RK3399_HCLK_HOST1		458
 #define RK3399_HCLK_HOST1_ARB		459
 #define RK3399_HCLK_SDMMC		462
+#define RK3399_HCLK_VOP0_NOC		472
+#define RK3399_HCLK_VOP0		473
+#define RK3399_HCLK_VOP1_NOC		474
+#define RK3399_HCLK_VOP1		475
 
 /* PMUCRU */