| Commit message (Collapse) | Author | Age | Files | Lines |
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Used by at least Skylake-SP (SKX) and Cascade Lake-SP (CLX).
Covers Xeon Scalable, Xeon D, Xeon W, Core Extreme/Core X product
families. The Scalable parts are marketed as Xeon Bronze, Silver, Gold
and Platinum.
As most of these ids are not described in public documents from Intel
use Skylake-ESystem.inf and KabyLakePCH-HSystem.inf from Intel's Windows
drivers to get an idea of what the names should be. With the name for
0x2088 found in a Intel authored Linux driver.
Initial patch and much discussion from Karel Gardas.
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also do the ethertype comparison before the conversion above.
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ok patrick@
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Starting right after unwind.
OK deraadt
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It should always run and there is no reload semantic.
OK deraadt
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OK deraadt@
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OK deraadt
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OK deraadt
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from servers.
dhcpleased(8) follows the well known three process design of all our
privsep daemons. It uses pledge(2) and unveil(2) to restrict access
further. In particular the "engine" process, responsible for parsing
of untrusted data, is pledge'd "stdio". It cannot access the outside
world nor the filesystem at all.
Like slaacd(8) for IPv6 it will be always running and acquire addresses
for all interface with the autoconf4 flag set.
The flag can be set by "ifconfig $if inet autoconf" or by adding
"inet autoconf" to /etc/hostname.if. An existing "dhcp" line should
be removed.
Various iterations tested by deraadt@
The hardest part, finding a name, was handled by jmatthew@ & otto@
"get to it :)" deraadt@
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If we're about to add a chain we have a trust path, so we have at least
one trusted certificate. This fixes a thinko from r1.31 and fixes the
openssl(1) cms verify test.
ok jsing (who had the same diff)
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nvram files used for the different Apple devices. The device tree and
the OTP hold the information which of those we will have to use. For
now this information will simply be printed, but depending on how we
choose to do the firmare distribution we could use it for loadfirmware().
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to use a different set of PCIE2REG registers. Accessing the "old" ones
even leads to faults. There are two surprises though. One is that it
seems that the interrupt status register always returns 0, and the other
one is that we receive the interrupts way too early, but both can be
worked around for now.
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advince from sthen@
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is passed to the IOMMU device driver.
ok patrick@
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this already on previous chips, which only started giving us packets when
handing over at least 128 of them. Apparently some now require 256, which
seems to get the Apple M1's WiFi going.
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ok patrick@
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OK phessler
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this avoids unecessary writes to memory. it helps a little bit with
a single nettq, but we get a lot more of a boost in pps when running
concurrently.
thanks to hrvoje for testing.
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check before using variable in list
remove unnecessary variable declaration
check value of adjustname()
add a '< 0' return value of snprintf
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with popular fuzzing drivers like libfuzzer. AFAIK nobody has used
it but me.
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ok florian@
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if the bridge is supposed to carry vlan packets, assuming it's an
s-vlan component and should allow certain group addresses to cross
between "customer" bridges.
i should probably let some of these groups fall back through to the
calling ether_input rather than drop them.
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testing has shown up to a 30% improvement in the veb forwarding
rate with this change.
an earlier diff was tested by hrvoje popovski
tested on amd64 and sparc64
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check value of adjustname()
use int for return value of snprintf
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the main bits are ether_addr_to_e64 and ether_e64_to addr for loading
an ethernet address into a uin64_t and visa versa. there's also
some macros for testing if an address in a uint64_t is multicast,
broadcast, anyaddr, or if it's an 802.1q reserved multicast group
address.
the reason for this functionality is once you have an ethernet
address as a uint64_t, operations like compares, bit tests, and
so on are fast and easy.
tested on amd64 and sparc64
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used in the wifi firmware to ensure responses can be received.
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ok dlg
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initialized.
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to load the CLM blob like the SDIO backend already does. Additionally it
is also helpful for the PCIe backend to try a file named after the device
tree compatible. Thus refactor the SDIO code and make it available for
both SDIO and PCIe.
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While the for-loop checks that thie value has changed since we wrote to
it, the timeout-condition checked for non-zero, which is wrong. This
means that we didn't realize the firmware wasn't started. While there,
make sure the shared DRAM address is inside the chip's address space.
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the same time.
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on the rx/tx complete rings has increased slightly to accomodate possible
new features.
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so that we can provide IOMMU-hooked bus DMA tags for each PCI device.
ok kettenis@
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mention that shell wildcards may be used.
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