wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

Age	Commit message (Expand)	Author	Files	Lines
2018-07-09	Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an	patrick	1	-3/+5
2016-08-10	Dynamically attach agtimer(4). Since agtimer(4) also provides the delay()	kettenis	1	-2/+2
2016-08-04	Dynamically attach ampintc(4) and make it register itself as an interrupt	kettenis	1	-2/+2
2016-05-02	Rework mainbus and implement simplebus to be able to span a tree-like	patrick	1	-2/+2
2013-09-09	Support for the ARM Generic Timer used in the Cortex-A7 and Cortex-A15.	patrick	1	-1/+5
2013-05-02	Add a driver for the secondary cache controller on the PandaBoard and	patrick	1	-1/+5
2013-05-01	Add a cortex bus which represents the ARM MPCore Complex.	patrick	1	-0/+14