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* Remove "for all XXX platforms" from comment. Fixes the issue pointed outkettenis2020-08-141-2/+2
| | | | | | by miod@ where the powerpc64 claimed to be "for all AArch64 platforms". ok patrick@
* Implement pci_intr_establish_cpu() on arm64 and armv7. The function pointerpatrick2020-07-141-3/+8
| | | | | | | | | | | | in the chipset tag for establishing interrupts now takes a struct cpu_info *. The normal pci_intr_establish() macro passes NULL as ci, which indicates that the primary CPU is to be used. The PCI controller drivers can then simply pass the ci on to our arm64/armv7 interrupt establish "framework". Prompted by dlg@ ok kettenis@
* Extend the interrupt API on arm64 and armv7 to be able to pass aroundpatrick2020-07-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix. Internally the "old" functions now call their *_cpu counterparts, passing NULL as ci. NULL will be interpreted as primary CPU in the interrupt controller code. The internal framework for interrupt controllers has been changed so that the establish methods provided by an interrupt controller function always takes a struct cpu_info *. Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt line for multiple pins. On those we simply disallow trying to establish an interrupt on a non-primary CPU, returning NULL. Since we do not have MP yet on armv7, all armv7 interrupt controllers do return NULL if an attempt is made to establish an interrupt on a different CPU. That said, so far there's no way this can happen. If we ever gain MP support, this is a reminder that the interrupt controller drivers have to be adjusted. Prompted by dlg@ ok kettenis@
* do not need these versions of timetc.hderaadt2020-07-081-23/+0
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* Add support for timeconting in userland.pirofti2020-07-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-56/+0
| | | | | | | | functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs.
* Add machdep.compatible.kettenis2020-05-171-2/+4
| | | | ok jsg@
* Let the armv7 bus_dma layer and simplebus(4) implementation deal withkettenis2020-04-291-24/+5
| | | | | | | | | | | DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of the hack for the Raspberry Pi in the dwctwo(4) driver. Note that this does not include the hack in simplebus(4) that we have on arm64 since firmware that has the dma-ranges is in widespread use now. ok patrick@
* Implement cpu_kick() and cpu_unidle().kettenis2020-01-121-2/+4
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* Convert boolean_t/TRUE/FALSE to int/1/0 for coherency with the rest ofmpi2019-12-191-5/+5
| | | | | | the kernel. ok patrick@
* Remove get_pc_str_offset(), which has been unused since we switchedpatrick2019-11-071-7/+1
| | | | | | | to clang, where the stack frame format changed significantly. Prompted by guenther@ noticing deprecated ASM warnings ok drahn@
* Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi2019-11-071-3/+3
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* Add code to spin up secondary CPUs.kettenis2019-10-271-1/+9
| | | | ok jsg@
* Synch the cpu match/attach/identify code with arm64. This drops somekettenis2019-09-302-25/+65
| | | | | | | | information from dmesg that is no longer relevant to ARMv7 CPUs in favour of printing the full architected cache hierarchy in the same way as we do on arm64. It also is another small step towards SMP support on armv7. ok patrick@
* Implement DVFS support.kettenis2019-09-231-1/+8
| | | | ok patrick@
* Store whether or not the VFP was active on entering the unhandledpatrick2019-03-132-3/+3
| | | | | | | | | instruction trap and pass it to the VFP fault handler, so that it knows if we faulted with the VFP active or disabled. Reading the status in the VFP fault handler does not work since at that point the VFP already got disabled. ok kettenis@
* flense more trailing whitespacephessler2019-01-221-5/+5
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* remove trailing whitespace in the Laptop Package part of the license text.phessler2019-01-221-4/+4
| | | | no words or punctation were modified.
* Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg2018-12-051-1/+2
| | | | | | | including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
* Unify the MD byteswapping code as much as possible across architectures.naddy2018-10-021-25/+20
| | | | | | | Use inline functions instead of GNU C statement expressions, and make them available to userland. With clues from guenther@. ok guenther@ kettenis@
* Unify and bump some of the NMBCLUSTERS defines. Some archs had it set toclaudio2018-09-141-2/+2
| | | | | | | | | 4MB which is far too low especially when the platform is able to run MP. New limits are, amd64 = 256M; arm64, mips64, sparc64 = 64M; alpha, arm, hppa, i386, powerpc = 32M; m88k, sh = 8M Still rather conservative numbers but much better than before. At least some hangs of arm64 build boxes was caused by this. OK kettenis@, visa@
* Extend the FDT interrupt API to support masking and unmasking IRQs.patrick2018-08-081-1/+3
| | | | Discussed with kettenis@
* Make it possible to build a MULTIPROCESSOR kernel on armv7. While thiskettenis2018-08-062-35/+39
| | | | | | | | doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup of <machine/cpu.h> along the lines of what I did earlier on arm64. Makes armv7 use the MI mplock implementation and implements copyin32. ok patrick@
* Give the FDT interrupt API a more generic naming by replacing thepatrick2018-08-061-1/+11
| | | | | | arm_intr_* prefix with fdt_intr_*. ok kettenis@
* Add PCI machdep headers based on the arm64 port.patrick2018-07-091-47/+37
| | | | ok kettenis@
* Remove strange /* End of file */ style.deraadt2018-06-306-18/+6
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* Save and restore FPU registers around signal handlers.kettenis2018-06-231-1/+5
| | | | | | Fixes the random crashes in sh(1). ok guenther@
* Save and restore the relevant FPU state on armv7.kettenis2018-06-221-35/+27
| | | | ok deraadt@
* Use speed from device tree for serial console on armv7 too.kettenis2018-05-071-1/+2
| | | | ok visa@, patrick@
* To allow sharing more code between armv7 and arm64 platforms, introducepatrick2018-03-201-1/+2
| | | | | | a common bus space tag that can be used for early console attachment. ok kettenis@
* Make FPU registers available in core dumps and through ptrace(2).kettenis2018-03-161-1/+1
| | | | ok visa@, patrick@
* Do not redefine PAGE_SHIFT/PAGE_SIZE/PAGE_MASK in vmparam.h; thosederaadt2018-03-051-9/+1
| | | | | definitions are already found in param.h ok jsg
* #define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archderaadt2018-03-051-1/+2
| | | | | | | | | | needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
* AAPCS requires 8-byte alignment for 64-bit types. We missed this when wekettenis2018-03-011-2/+2
| | | | | | | | | | | | did the big EABI switch. Do it now before we get into trouble with using floating-point and vector instructions that actually require things to be properly aligned. This breaks the ABI. In particular, file descriptor passing will be broken if kernel and userland are not in sync. Upgrading from a snap is highly recommended. ok otto@, patrick@, jsg@, phessler@, deraadt@
* Convert armv7 to MI mutex.mpi2018-02-101-72/+2
| | | | Tested by jsg@, ok patrick@
* Add kernel support for the VFP FPU/SIMD unit. Based on a diff by drahn@.kettenis2018-01-264-19/+144
| | | | | | | | | This allows us to use floating-pointer and vector instructions in userland code. The current implementation assumes all 32 VFP registers are present. This should be the case on all armv7 hardware currently supported by OpenBSD. ok patrick@
* Revise 'struct fpreg' such that it can actually represent the full VFPv3-D32kettenis2018-01-231-5/+3
| | | | | | state. ok patrick@
* Improve defense against branch predictor target injection (Spectre "variant 2")kettenis2018-01-152-2/+7
| | | | | | | | | | | | | | | | | | attacks. OpenBSD/armv7 is already in pretty good shape as we have always been flushing the branch predictor cache on context switches. This diff adds additional flushes to page faults in kernel address space. The impact on performance should be minimal as these page faults should only happen when userland (deliberately or accidentally) tries to access kernel addres space which would lead to a fatal signal (SIGSEGV or SIGBUS). Loosely based on changes made by Marc Zyngier in Linux and based on information in Arm Trusted Firmware Security Advisory TFV 6. Note that for Cortex-A15 (and Cortex-A72) you will need firmware that sets the ACTRL[0] bit for this diff to be effective. Also note that with this diff Cortex-A57 is still vulnerable. ok jsg@
* set MAXSSIZ to the same value as on all other architectures (32MB)naddy2017-10-011-2/+2
| | | | ok deraadt@
* Move mutex, condvar, and thread-specific data routes, pthread_once, andguenther2017-09-051-5/+1
| | | | | | | | pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
* Add glass console support for arm64. This uses the "stdout-path" propertykettenis2017-08-271-1/+5
| | | | | | | | | of the /chosen node in the device tree to decide whether the framebuffer should be used as the console device. Most, if not all, machines will have that set to use a serial console and there is no easy way yet to change that. ok jsg@
* Add Cortex-A55 and Cortex-A75 part numbers.jsg2017-08-201-1/+5
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* remove apmwarn sysctl which is not usedtedu2017-08-121-3/+3
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* Use unsigned long instead of uint32_t, which is the appropriate integerkettenis2017-07-311-3/+3
| | | | | | | type for storing pointers in our universe. Avoids an implicit dependence on <sys/types.h>. ok tom@
* remove CPU_LIDSUSPEND/machdep.lidsuspendnatano2017-07-121-3/+3
| | | | "fire away!" tedu
* kill RCSID macros; discussed with millertderaadt2017-06-291-5/+1
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* Unbreak profiling assembly functions in userland by defining thempi2017-06-231-2/+2
| | | | | | correct prologue if compiled with -DPROF. ok deraadt@
* Fix kernel build on armv7 and sh.visa2017-05-181-2/+2
| | | | Pointed out by deraadt@
* Make atomic.h ready to be included in userland.mpi2017-05-121-39/+40
| | | | | - keep setbits/clearbits and virtio barriers inside _KERNEL - prefix def_atomic_xxx macros with underscores
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