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* Refactor the MAP_STACK feature, and introduce another similar variation:deraadt2019-06-011-19/+4
| | | | | | | | | Lookup the address that a syscall instruction is executed from, and kill the process if that page is writeable. This brings an aspect of W^X behaviour to W|X mappings (in JITs not yet adapted to W^X). The goal is to remove simple attack methods and force use of ret2libc or other more complicated means. ok kettenis stefan visa
* Prevent attaching drivers to devices for which we attached a driver early.kettenis2019-04-162-4/+24
| | | | ok patrick@, dlg@, visa@
* Store whether or not the VFP was active on entering the unhandledpatrick2019-03-135-22/+26
| | | | | | | | | instruction trap and pass it to the VFP fault handler, so that it knows if we faulted with the VFP active or disabled. Reading the status in the VFP fault handler does not work since at that point the VFP already got disabled. ok kettenis@
* revert revert revert. there are many other archs that use custom allocs.tedu2019-02-101-3/+3
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* make it possible to reduce kmem pressure by letting some pools use a moretedu2019-02-101-3/+3
| | | | | | | | | | accomodating allocator. an interrupt safe pool may also be used in process context, as indicated by waitok flags. thanks to the garbage collector, we can always free pages in process context. the only complication is where to put the pages. solve this by saving the allocation flags in the pool page header so the free function can examine them. not actually used in this diff. (coming soon.) arm testing and compile fixes from phessler
* Add .fpu directives in inline assembly to silence new compilerkettenis2019-01-241-3/+9
| | | | | | | | warnings/errors about using VFP2 instructions. We use vfpv3 here (which corresponds to vfpv3-d32) since that is the minimum requirement for OpenBSD/armv7. ok jsg@, patrick@
* flense more trailing whitespacephessler2019-01-221-5/+5
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* remove trailing whitespace in the Laptop Package part of the license text.phessler2019-01-221-4/+4
| | | | no words or punctation were modified.
* match arm64 and print unconfigured simplebus devices on armv7jsg2019-01-051-2/+23
| | | | ok dlg@ kettenis@
* For shared interrupts we need to make sure that we registerpatrick2018-12-071-7/+9
| | | | | | | | with the lowest IPL. Once we actually run the IRQ handler we raise to the highest IPL. Fixes a crash seen when having a network card in the PCIe slot of the MacchiatoBin. ok ccardenas@
* Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg2018-12-051-1/+2
| | | | | | | including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
* Unify the MD byteswapping code as much as possible across architectures.naddy2018-10-021-25/+20
| | | | | | | Use inline functions instead of GNU C statement expressions, and make them available to userland. With clues from guenther@. ok guenther@ kettenis@
* Unify and bump some of the NMBCLUSTERS defines. Some archs had it set toclaudio2018-09-141-2/+2
| | | | | | | | | 4MB which is far too low especially when the platform is able to run MP. New limits are, amd64 = 256M; arm64, mips64, sparc64 = 64M; alpha, arm, hppa, i386, powerpc = 32M; m88k, sh = 8M Still rather conservative numbers but much better than before. At least some hangs of arm64 build boxes was caused by this. OK kettenis@, visa@
* fix whitespacejsg2018-09-061-3/+3
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* Use MAXCPUS as the number of elements for the array of per-cpu data.kettenis2018-08-111-4/+2
| | | | ok jsg@, patrick@
* Extend the FDT interrupt API to support masking and unmasking IRQs.patrick2018-08-081-1/+3
| | | | Discussed with kettenis@
* Make it possible to build a MULTIPROCESSOR kernel on armv7. While thiskettenis2018-08-0622-79/+165
| | | | | | | | doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup of <machine/cpu.h> along the lines of what I did earlier on arm64. Makes armv7 use the MI mplock implementation and implements copyin32. ok patrick@
* Give the FDT interrupt API a more generic naming by replacing thepatrick2018-08-061-1/+11
| | | | | | arm_intr_* prefix with fdt_intr_*. ok kettenis@
* Move from sendsig() to its callers the initsiginfo() calls andguenther2018-07-101-10/+8
| | | | | | | | instead of passing sendsig() the code+type+val, pass a siginfo_t* to copy from. Eliminate the indirection through struct emul for sendsig(); we no longer have a SunOS4-compat version of sendsig() ok deraadt@
* Add PCI machdep headers based on the arm64 port.patrick2018-07-091-47/+37
| | | | ok kettenis@
* Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is anpatrick2018-07-093-18/+180
| | | | | | | | | | | | | | | | | | | extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI. Implement support for interrupt types. The GIC only seems to support level triggered active-high or egdge triggered low-to-high interrupts. We currently always configure them to be level triggered, which is a sane default for most controllers. Since MSI interupts on the GIC are edge triggered, we need to be able to parse the type information and to configure the interrupt correspondingly. ok kettenis@
* Remove strange /* End of file */ style.deraadt2018-06-3013-40/+13
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* Make ast() call refreshcreds(). Tweak this code to be similar to the amd64.kettenis2018-06-261-15/+3
| | | | ok phessler@, guenther@
* Save and restore FPU registers around signal handlers.kettenis2018-06-232-4/+32
| | | | | | Fixes the random crashes in sh(1). ok guenther@
* Move up the setting of pcb_tf, refreshcreds(), and stack check so thatguenther2018-06-221-28/+26
| | | | | | | we can be sure signals posted from userret() are based on the correct information ok kettenis@
* Update the pointer to the trapframe in the PCB when handling an AST.kettenis2018-06-221-1/+3
| | | | From drahn@, ok guenther@
* Save and restore the relevant FPU state on armv7.kettenis2018-06-221-35/+27
| | | | ok deraadt@
* Remove the cpu_reset_needs_v4_MMU_disable flag; it's always true for hardwarekettenis2018-06-042-26/+6
| | | | | | that OpenBSD runs on. ok patrick@
* Remove #ifdef __XSCALE__ bits. No binary change.kettenis2018-06-035-279/+5
| | | | ok deraadt@
* Remove a4x bus space hack.kettenis2018-05-154-240/+1
| | | | ok patrick@
* Use speed from device tree for serial console on armv7 too.kettenis2018-05-071-1/+2
| | | | ok visa@, patrick@
* Add a common rules file for ofw sources to help keep the configurationsvisa2018-05-041-2/+2
| | | | | | of fdt-enabled platforms in sync. OK deraadt@
* Implement MAP_STACK option for mmap(). Synchronous faults (pagefault andderaadt2018-04-122-4/+24
| | | | | | | | | | | | | | syscall) confirm the stack register points at MAP_STACK memory, otherwise SIGSEGV is delivered. sigaltstack() and pthread_attr_setstack() are modified to create a MAP_STACK sub-region which satisfies alignment requirements. Observe that MAP_STACK can only be set/cleared by mmap(), which zeroes the contents of the region -- there is no mprotect() equivalent operation, so there is no MAP_STACK-adding gadget. This opportunistic software-emulation of a stack protection bit makes stack-pivot operations during ROPchain fragile (kind of like removing a tool from the toolbox). original discussion with tedu, uvm work by stefan, testing by mortimer ok kettenis
* To allow sharing more code between armv7 and arm64 platforms, introducepatrick2018-03-202-2/+4
| | | | | | a common bus space tag that can be used for early console attachment. ok kettenis@
* Do not panic from ddb(4) when a lock requirement isn't fulfilled.mpi2018-03-201-3/+1
| | | | | | | | | | | Extend the logic already present for panic() to any DDB-related operation such that if ddb(4) is entered because of a fault or other trap it is still possible to call 'boot reboot'. While here stop printing splassert() messages as well, to not fill the buffer. ok visa@, deraadt@
* Make FPU registers available in core dumps and through ptrace(2).kettenis2018-03-165-13/+29
| | | | ok visa@, patrick@
* Rework and cleanup the linker script for armv7. The main feature ispatrick2018-03-081-43/+46
| | | | | | | | | that it gives us a read-only data section. In addition the linker script is now easily diffable to arm64 and we also stop mapping some unnecessary space before the kernel. Prompted by deraadt@ ok kettenis@
* Do not redefine PAGE_SHIFT/PAGE_SIZE/PAGE_MASK in vmparam.h; thosederaadt2018-03-051-9/+1
| | | | | definitions are already found in param.h ok jsg
* #define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archderaadt2018-03-051-1/+2
| | | | | | | | | | needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
* AAPCS requires 8-byte alignment for 64-bit types. We missed this when wekettenis2018-03-011-2/+2
| | | | | | | | | | | | did the big EABI switch. Do it now before we get into trouble with using floating-point and vector instructions that actually require things to be properly aligned. This breaks the ABI. In particular, file descriptor passing will be broken if kernel and userland are not in sync. Upgrading from a snap is highly recommended. ok otto@, patrick@, jsg@, phessler@, deraadt@
* Explicitly align svcstack and esym. Finally fixes the problem wherekettenis2018-02-281-1/+3
| | | | | | | kernels wouldn't boot because the random order in which we happened to link it would cause these symbols to be misaligned. Thanks to Brandon Bergren for figuring out the problem.
* Typo: auxilliary -> auxiliaryguenther2018-02-251-2/+2
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* Get rid of the cpu_on_fn hook and call the psci(4) functions directly insteadkettenis2018-02-231-3/+1
| | | | | | like we already do in the code that flushes the BTB. ok jsg@
* Remove almost unused `flags' argument of suser().mpi2018-02-191-3/+3
| | | | | | | The account flag `ASU' will no longer be set but that makes suser() mpsafe since it no longer mess with a per-process field. No objection from millert@, ok tedu@, bluhm@
* Rework the DDB trace handling for armv7. By switching to clang thepatrick2018-02-111-64/+12
| | | | | | | | stack frame format has changed. Apparently AAPCS doesn't specify at all what a stack frame looks like. We end up with much simpler code, but also with a lot less information in the trace. ok kettenis@
* Convert armv7 to MI mutex.mpi2018-02-103-168/+3
| | | | Tested by jsg@, ok patrick@
* Replace two spaces indents with tabs. Makes it easier to read andpatrick2018-02-101-72/+72
| | | | | | especially makes it easier to diff against our other linker scripts. ok jsg@
* Supplying entropy from etext has created a regression on arm where wepatrick2018-02-101-1/+2
| | | | | | | | | get an alignment fault while copying the data. Turns out that since we have .rodata in the text segment, it's very easily possible that etext remains unaligned. Work around this by word-aligning etext. The next step is to split .rodata out of the text segment. ok deraadt@
* Put the ldscript parts into a single file instead of storing it as headpatrick2018-02-102-27/+25
| | | | | | | and tail and cat(1) it together. It was maybe needed when ports needed different contents, but now it's just a headache. ok deraadt@
* Make sure sigfillsiz is word aligned.patrick2018-02-061-1/+2
| | | | ok kettenis@
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