| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-05-31 | introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c. |   dlg | 1 | -1/+3 |
| 2019-09-02 | in non-MP, cpu_number() the #define should be 0UL; ok visa |   deraadt | 1 | -2/+2 |
| 2019-05-05 | Turn need_resched() and signotify() into proper functions on mips64. |   visa | 1 | -12/+3 |
| 2018-12-05 | Include srp.h where struct cpu_info uses srp to avoid erroring out when |   jsg | 1 | -1/+2 |
| 2018-12-04 | Add processor IDs for several OCTEON II and III SoCs. | visa | 1 | -1/+5 |
| 2018-02-24 | Declare ci_ipl volatile to prevent the compiler from optimizing | visa | 1 | -2/+2 |
| 2018-01-29 | Drop unused field `ci_ipiih'. | visa | 1 | -2/+1 |
| 2017-10-21 | Use MI mplock on mips64. | visa | 1 | -1/+13 |
| 2017-09-02 | Let the kernel utilize the FPU if one is available, even when the | visa | 1 | -1/+7 |
| 2017-07-30 | Define MAXCPUS per mips64 port. | visa | 1 | -2/+1 |
| 2017-07-12 | remove CPU_LIDSUSPEND/machdep.lidsuspend |   natano | 1 | -3/+3 |
| 2017-06-11 | Fix TLB size computation on OCTEON II and III. The CPUs have utilized | visa | 1 | -1/+2 |
| 2017-05-24 | Add an idle cycle implementation for R4600/R5000/RM7000 CPUs and their | visa | 1 | -1/+4 |
| 2017-04-20 | Make TCB address available to userspace via the UserLocal register. | visa | 1 | -1/+27 |
| 2017-04-07 | Add prid for CN72xx/CN73xx. | visa | 1 | -1/+2 |
| 2017-03-02 | Add a new sysctl machdep.lidaction. The sysctl works as follows: | natano | 1 | -2/+4 |
| 2016-12-17 | Make Octeon model strings a bit more specific. While there, | visa | 1 | -3/+4 |
| 2016-12-16 | Provide the "machdep.lidsuspend" sysctl on Loongson. |   fcambus | 1 | -2/+4 |
| 2016-08-14 | Utilize the TLB Execute-Inhibit bit with non-executable mappings on CPUs | visa | 1 | -1/+3 |
| 2016-03-06 | Rename mips64's trap_frame into trapframe. |   mpi | 1 | -9/+9 |
| 2016-03-01 | guard macro args with parens |   mmcc | 1 | -3/+3 |
| 2016-01-05 | Some implementations of HitSyncDCache() call pmap_extract() for va->pa | visa | 1 | -1/+7 |
| 2015-12-25 | Make interrupt masking MP-aware. Linux IP27 and IP35 ports served as a | visa | 1 | -1/+7 |
| 2015-09-23 | That PICA reference ought to have been removed 20 years ago! |   miod | 1 | -2/+2 |
| 2015-07-02 | introduce srp, which according to the manpage i wrote is short for | dlg | 1 | -1/+5 |
| 2015-02-11 | no md code wants lockmgr locks, so no md code needs to include sys/lock.h | dlg | 1 | -2/+1 |
| 2014-08-14 | fixed overrid(d)en typo |   tobias | 1 | -2/+2 |
| 2014-07-11 | CPU_BUSY_CYCLE(): A new MI statement for busy loop power reduction |   uebayasi | 1 | -1/+3 |
| 2014-04-04 | Second step of the R4000 EOP errata WAR: when pmap invalidates a page which | miod | 1 | -1/+2 |
| 2014-03-31 | Due the virtually indexed nature of the L1 instruction cache on most mips | miod | 1 | -2/+13 |
| 2014-03-29 | It's been a quarter century: we can assume volatile is present with that name. |   guenther | 1 | -3/+3 |
| 2014-03-22 | Second draft of my attempt to workaround the infamous R4000 end-of-page errata, | miod | 1 | -1/+13 |
| 2014-03-21 | Rename db_inst_type() into classify_insn() and make that function available | miod | 1 | -1/+6 |
| 2014-03-09 | Rework the per-cpu cache information. Use a common struct to store the line | miod | 1 | -11/+16 |
| 2013-12-19 | recognize octeon 2 cpus; as found in the lanner mr326 |   jasper | 1 | -1/+2 |
| 2013-03-12 | Fix kernel profiling on MP systems by using per-CPU buffers and teach | mpi | 1 | -1/+4 |
| 2013-02-12 | Back out per-CPU kernel profiling, it shouldn't modify a public header | mpi | 1 | -4/+1 |
| 2013-02-11 | Fix kernel profiling on MP systems by using per-CPU buffer. Previously | mpi | 1 | -1/+4 |
| 2012-12-02 | Determine whether we're currently on the alternative signal stack | guenther | 1 | -1/+2 |
| 2012-10-03 | Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs, | miod | 1 | -264/+24 |
| 2012-09-29 | Basic R8000 processor support. R8000 processors require MMU-specific code, | miod | 1 | -3/+72 |
| 2012-09-29 | Forgot this in previous commit | miod | 1 | -1/+3 |
| 2012-09-29 | Handle the coprocessor 0 cause and status registers as a 64 bit value now, | miod | 1 | -14/+17 |
| 2012-09-29 | Add a few more coprocessor 0 cause and config registers defines. | miod | 1 | -41/+54 |
| 2012-09-29 | Kill the mostly unused VMTLB_xxx and VMNUM_xxx defines. Move all tlb | miod | 1 | -42/+7 |
| 2012-09-29 | Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of | miod | 1 | -1/+3 |
| 2012-07-14 | Split the existing mips64 clock code into time-of-day and generic duties in | miod | 1 | -2/+12 |
| 2012-06-24 | Add cache operation functions pointers to struct cpu_info; the various | miod | 1 | -2/+48 |
| 2012-05-27 | Add a `L2 cache line size' member to struct cpu_info. This allows R4k code to | miod | 1 | -1/+2 |
| 2012-04-19 | Print the currently active ASID in `machine tlb' ddb command. | miod | 1 | -2/+3 |
