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2020-06-05cpu_rnd_messybits() for mips64visa1-1/+13
2020-05-31introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg1-1/+3
2020-05-29dev/rndvar.h no longer has statistical interfaces (removed during variousderaadt1-2/+1
2020-05-27Retire <machine/varargs.h>.visa1-50/+0
2020-05-23Use a distinct trap code with retguard on mips64.visa1-1/+9
2020-05-16Make inittodr() and resettodr() MI.kettenis1-91/+1
2020-05-16Use todr_gettime() in cp0_calibrate() on mips64.visa1-11/+13
2020-05-11Initialize the timeval passed to todr_gettime() with the base time fromkettenis1-10/+5
2020-05-09Use the same inittodr()/resettodr() implementation as onkettenis1-135/+158
2020-04-18Sync existing stacktrace_save() implementationsvisa1-4/+8
2020-01-20Separate the stack trace saving interface from ddb. The saving does notvisa1-3/+4
2020-01-02Use newabi register names in disassembly.visa1-3/+3
2019-12-20Convert various boolean_t/TRUE/FALSE to int/1/0 in mips64 memory code.visa3-7/+7
2019-12-20Convert boolean_t/TRUE/FALSE to int/1/0 in mips64 pmap.visa1-46/+46
2019-11-20Ensure that the kernel stack is properly aligned on mips64. This fixesvisa1-2/+2
2019-11-07Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi3-15/+14
2019-11-07Substitute boolean_t/TRUE/FALSE by int/1/0.mpi3-13/+13
2019-10-28Fix atomic_sub_long_nv() on mips64. The negation should usevisa1-2/+2
2019-09-06Do not stop prologue scan at branch instructions. This lets stack tracevisa1-3/+2
2019-09-06Stop stack trace saving if the current subroutine is u_general or u_intrvisa1-3/+4
2019-09-06If uvm_map_inentry returns false then a signal has been delivered, andderaadt1-3/+3
2019-09-05Implement splassert() on mips64.visa1-1/+15
2019-09-05Adjust interrupt priority levels on mips64 so that prioritiesvisa2-6/+3
2019-09-02cpu number is unsigned (does not really matter)deraadt1-2/+2
2019-09-02in non-MP, cpu_number() the #define should be 0UL; ok visaderaadt1-2/+2
2019-08-21Fix a race in invalidation of remote TLB entries.visa3-13/+38
2019-08-02Avoid repeated invocation of curcpu().visa1-2/+2
2019-08-02Call refreshcreds() from ast() on mips64. This ensures that credentialsvisa1-1/+2
2019-07-09I wrote the pc-page-writeable and sp-not-MAP_STACK code to be shared, andderaadt1-2/+3
2019-06-30Ansify function definitions.visa1-10/+4
2019-06-23Invalidate icache when changing mappingvisa1-21/+51
2019-06-01Refactor the MAP_STACK feature, and introduce another similar variation:deraadt1-21/+4
2019-05-15Reduce branch emulation page access protection during setup. The setupvisa1-3/+3
2019-05-15Drop redundant pmap_proc_iflush() call. The needed instruction cachevisa1-2/+1
2019-05-08Print the current ASID in hex instead of decimal, to match the formatvisa1-2/+2
2019-05-06Enforce store/load order when setting or clearing AST flag on mips64visa3-3/+22
2019-05-06Issue write-write barrier before sending IPI on mips64visa1-10/+25
2019-05-06Fix unintentional delay of ASTs on MP mips64visa1-23/+29
2019-05-05Call cpu_unidle() from need_resched() on mips64 like mostvisa1-2/+4
2019-05-05Turn need_resched() and signotify() into proper functions on mips64.visa3-14/+21
2019-04-26Guard against repeated inclusion of <mips64/pte.h>. This fixes drm buildvisa1-1/+6
2019-04-23Call exit(2) if sigreturn(2) fails on mips64. This is what othervisa1-2/+3
2019-04-19Work around a limitation of clang integrated assembler on mips64.visa1-1/+2
2019-03-23Use the debugger mutex for `ddb_mp_mutex'. This should prevent a racevisa2-19/+17
2019-03-17Move intr_barrier(9) to the platform level so that it can be customized.visa1-7/+1
2019-03-16Include header <sys/evcount.h> where event counters are used, so thatvisa2-5/+7
2019-01-14Wrap floating point instructions with .set hardfloat to make clang'svisa2-6/+31
2019-01-05Expand a macro instruction for clang. Unlike gas, the integratedvisa1-2/+3
2019-01-05Replace two-operand instruction aliases that clang does notvisa1-2/+2
2018-12-31Set floating point condition code even if the result of an emulatedvisa1-6/+6
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