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* Make it clearer where message "spurious interrupt" comes from.visa2019-09-011-3/+5
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* Let each interrupt controller driver choose how to implementvisa2019-03-171-2/+13
| | | | | | | intr_barrier(9). With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
* Include header <sys/evcount.h> where event counters are used, so thatvisa2019-03-161-1/+2
| | | | header <machine/intr.h> can eventually stop including it on octeon.
* Assume edge triggering by default for robustness, as is donevisa2017-07-311-2/+2
| | | | in octcit(4).
* Add a driver for the CIB interrupt controller. Certain devicevisa2017-07-131-0/+314
controllers need it on CN70xx/CN71xx.