| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Let each interrupt controller driver choose how to implement |   visa | 2019-03-17 | 1 | -2/+5 |
| | | | | | | | | intr_barrier(9). With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores. | ||||
| * | Move intr_barrier(9) to the platform level so that it can be customized. | visa | 2019-03-17 | 1 | -1/+7 |
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| * | Unify the top-level structure of interrupt handles. This helps | visa | 2019-03-16 | 1 | -8/+26 |
| | | | | | when implementing interrupt-specific logic for intr_barrier(9). | ||||
| * | Split octeon interrupt code into a glue layer and a CIU driver. | visa | 2017-06-18 | 1 | -398/+61 |
| | | | | | | | | This makes possible to add drivers for other interrupt controllers on the platform. The glue layer has been derived from arm64/armv7. | ||||
| * | Move IPI control entry points into octeon_intr.c. | visa | 2017-06-18 | 1 | -1/+68 |
| | | | | | Needed by upcoming driver changes. | ||||
| * | Extend the fdt interrupt API a little. | visa | 2017-04-06 | 1 | -1/+15 |
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| * | Add a routine for setting up interrupt handlers using fdt. | visa | 2016-12-08 | 1 | -1/+32 |
| | | | | | ok kettenis@ | ||||
| * | Add handling for the second interrupt bank. | visa | 2016-12-04 | 1 | -29/+73 |
| | | | | | Needed by an upcoming driver. | ||||
| * | Implement octeon_intr_disestablish(). | visa | 2016-12-03 | 1 | -4/+32 |
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| * | Drop stale prototypes and an outdated comment. | visa | 2016-12-02 | 1 | -7/+1 |
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| * | Simplify interrupt dispatching by processing requests without | visa | 2016-12-02 | 1 | -74/+73 |
| | | | | | prioritization by IPL. | ||||
| * | Drop pointless type casts. | visa | 2016-11-20 | 1 | -9/+6 |
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| * | Add $OpenBSD$ / replace $Id$ with $OpenBSD$. | visa | 2016-07-16 | 1 | -0/+2 |
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| * | Rename mips64's trap_frame into trapframe. |   mpi | 2016-03-06 | 1 | -3/+3 |
| | | | | | | | For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@ | ||||
| * | xheart_splx() has to restore the interrupt mask even on secondary CPUs | visa | 2015-09-26 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | because each core has a separate mask. Otherwise the IPI can be left disabled accidentally on a non-primary CPU when the core uses the rendezvous mutex: 1. splraise(IPL_IPI) soft-masks the IPI. 2. An IPI hits and the CPU enters the interrupt handler. 3. The handler hard-masks the IPI. 4. The interrupt is not processed because of the CPU's current IPL. The IPI is left hard-masked on leaving the handler. 5. splx(s) lowers the IPL below IPL_IPI. However, the interrupt's hardware mask is left unchanged because of the CPU_IS_PRIMARY() check in xheart_splx(). After this, the system will eventually hang because the CPU does not respond to IPI requests of other cores. While here, fix a similar situation with CIU interrupts on octeon. This might save a few moments of debugging once non-primary CPUs are allowed to process CIU interrupts. ok miod@ | ||||
| * | Let MP-safe interrupt handlers run without the kernel lock on octeon. | visa | 2015-09-26 | 1 | -6/+16 |
| | | | | | ok kettenis@ | ||||
| * | Do not grab the kernel lock for clock interrupts. Help and ok kettenis@ |   miod | 2015-05-01 | 1 | -2/+2 |
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| * | implement atomic operations using ll/sc, and convert rw_cas and callers of the |   jmatthew | 2014-09-30 | 1 | -2/+3 |
| | | | | | | | | pre-existing atomics to match. tested on sgi (octane) and octeon (erl) ok miod@ dlg@ | ||||
| * | move octeonreg.h to a more generic location and add multiple inclusion |   jasper | 2013-06-02 | 1 | -1/+1 |
| | | | | | | | guards while here. ok uebayasi@ | ||||
| * | Don't include <mips64/archtype.h> when you don't need it. | miod | 2012-10-03 | 1 | -1/+0 |
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| * | Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs, | miod | 2012-10-03 | 1 | -0/+1 |
| | | | | | | | | which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the goriest md details, which are only of interest to a handful set of files; this is similar in spirit to what alpha does, but here <machine/cpu.h> does not include the new file. | ||||
| * | Handle the coprocessor 0 cause and status registers as a 64 bit value now, | miod | 2012-09-29 | 1 | -1/+1 |
| | | | | | | as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used. | ||||
| * | Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of | miod | 2012-09-29 | 1 | -3/+6 |
| | | | | | such statements with it. | ||||
| * | Remove leftover loongson or sgi references. | miod | 2012-06-17 | 1 | -1/+1 |
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| * | obio renamed iobus, moved interrupt handler code to dev/octeon_intr.c |   syuu | 2011-05-08 | 1 | -0/+323 |
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index : wireguard-openbsd | |
| WireGuard implementation for the OpenBSD kernel | Matt Dunwoodie |
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