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* OPAL implements firmware calls that abstract communicating with the BMC overkettenis2021-01-232-1/+296
| | | | | | IPMI. Use these calls to add support for impi(4) on PowerNV systems. ok dlg@
* Enable support for floating-point exceptions. We always run in "precise"kettenis2021-01-093-3/+7
| | | | | | | | | | | | mode. On modern processors (POWER8 and later) there is no performance penalty for this as long as exceptions are disabled in the FPSCR (which is the default). This way we don't have to implement an architecture-dependent system call to set the mode, as it can only be done by the kernel. With help from gkoehler@ ok gkoehler@
* Enter power-saving mode on POWER9 (ISA v3)gkoehler2020-12-303-3/+10
| | | | | | | | | | | | | | | | | | | When opal(4) attaches, look in the device tree for a psscr value. In cpu_idle_cycle(), use this psscr value and the stop instruction to wait for the next interrupt. In mp kernels, cpu_unidle() now sends an interrupt. In "sysctl hw.sensors", the power and temperature sensors from opalsens(4) may show lower values. The cpu may exit stop at the system reset vector after losing user registers. If so, restore some registers. For now, ignore deeper stop states that would lose hypervisor registers. Our mp kernel uses only the first hardware thread of each core. Take the extra threads from the firmware and stop them forever; this may switch the core from SMT4 to single-thread mode and increase performance. partly by kettenis@, ok kettenis@
* Clear FSCR register. This gives us a sane default state where all facilitieskettenis2020-12-221-1/+7
| | | | are disabled by default on all CPUs.
* Hardwire bus_space_read_raw_N() and bus_space_write_raw_N() tokettenis2020-11-151-7/+7
| | | | | generic_space_read_N() and generic_space_write_N() as they should not do any byte swapping.
* Add code to determine the console devie node.kettenis2020-10-301-1/+4
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* Add forward declaration of struct trapframe.kettenis2020-10-241-1/+2
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* Add retguard to OPAL functions in powerpc64 locore.mortimer2020-10-221-7/+7
| | | | ok deraadt@ kettenis@
* Only use OPAL_CONSOLE_FLUSH if the firmware implements it. Should helpkettenis2020-10-191-1/+2
| | | | on POWER8 machines with older versions of OPAL.
* use the full 64-bit cookies, rather than just 32 bitsderaadt2020-10-171-3/+3
| | | | spotted by gkoehler, ok mortimer
* Add retguard asm macros for ppc64.mortimer2020-10-161-1/+39
| | | | ok deraadt@
* Add OPAL_PCI_MAP_PE_DMA_WINDOW.kettenis2020-10-101-1/+4
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* Use an IPI, so hw.setperf affects all cores in the mp kernel.gkoehler2020-09-232-3/+7
| | | | | | | | | | Before, apm -A was speeding up only one core of my POWER9. Now, apm -A speeds up all cores, so my parallel builds are faster. I copy the idea from amd64 and i386: mp_setperf() sends an IPI to all cpus; the interrupt handler calls ul_setperf(). ok deraadt@ kettenis@
* Correctly pass the "struct cpu_info" pointer along when establishingkettenis2020-09-212-6/+11
| | | | | | | | interrupts. This fixes IPIs on machines with certain (newer?) OPAL firmware. It also allows implementing pci_intr_establish_cpu(9), which is needed for distributing interrupt handlers across CPUs. tested by gkoehler@
* Stop using %r13 as the per-cpu register in the kernel. Sincekettenis2020-09-151-3/+8
| | | | | | uvm_map_inentry() may sleep we would have to do the same fixup as after calling uvm_fault() there. It is just simpler and safer to just rely on the pointer in SPRG0.
* Add a proper VSID allocation scheme for userland segments.kettenis2020-09-071-1/+3
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* Implement spilling of kernel SLB entries. Mostly from FreeBSD.kettenis2020-09-053-3/+6
| | | | | | | | | | | | | This makes it possible to use more SLB entries for the kernel than the hardware supports. The design is such that a subset of the hardware SLB entries can be replaced when needed. This makes sure the entries mapping kernel code and data and the page tables ar always present. Traps for missing SLB entries are handled in real-mode and on a special stack such that it doesn't have to rely on SLB entires mapping kernel stacks. With this in place we can increase KVA to 32GB. Hopefully that's enough to support large memory configurations.
* Restrict the size of the page table to 2G such that it never occupies morekettenis2020-09-041-2/+2
| | | | than 8 SLB entries.
* Make the kernel address space a bit bigger.kettenis2020-09-041-1/+1
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* Fix signotify() for powerpc64 bsd.mpgkoehler2020-09-011-4/+3
| | | | | | | Copy signotify() from amd64, so that if proc *p is on another cpu, then signotify(p) notifies the correct cpu. ok kettenis@
* Store the device tree node in the pcitag_t.kettenis2020-09-011-1/+4
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* Clear user SLB upon context switch.kettenis2020-08-251-1/+2
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* Add support for "normal" external interrupts. Needed for running on POWER8kettenis2020-08-231-1/+2
| | | | and earlier CPUs.
* Add OPAL_SET_XIVE and OPAL_GET_XIVE.kettenis2020-08-231-13/+17
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* Add support for POWER8 (and maybe earlier) CPUs. Not sure if this works onkettenis2020-08-232-2/+20
| | | | | | | | | | real hardware, but it gets the kernel booting on QEMU emulating a POWER8 CPU so it's a step in the right direction. This establishes a way to distinguish CPU features based on the AT_HWCAP and AT_HWCAP2 features documented in the ELF ABI. Also use this to determine the availability of the DARN instruction instead of keying of the processor model.
* Switch to a per-proc SLB cache. Seems to make GENERIC.MP kernelskettenis2020-08-172-3/+4
| | | | | (much more) stable. Probably because we could restore an incoherent SLB cache since there was no locking in the trap return path.
* Remove "for all XXX platforms" from comment. Fixes the issue pointed outkettenis2020-08-141-2/+2
| | | | | | by miod@ where the powerpc64 claimed to be "for all AArch64 platforms". ok patrick@
* Bump MAXCPUS (for MULTIPROCESSOR kernels) to 48, which seems to be thekettenis2020-07-231-2/+2
| | | | maximum numbers of cores available in any POWER9 system.
* Use per-pmap lock to protect userland SLB handling.kettenis2020-07-231-4/+2
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* Make switching CPUs in DDB work.kettenis2020-07-223-5/+28
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* Implement IPIs.kettenis2020-07-222-6/+15
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* Add missing mplock.h file.kettenis2020-07-221-0/+10
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* Add code to spin up the secondary CPUs.kettenis2020-07-211-4/+46
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* Add OPAL_START_CPU.kettenis2020-07-211-1/+3
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* Make pmap ready for GENERIC.MP.kettenis2020-07-211-1/+2
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* Use the same names as the 64-bit PowerPC ELF ABI for the relocations.kettenis2020-07-181-117/+141
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* Pass boothowto and bootduid parameters to the booted kernel via thekettenis2020-07-181-5/+5
| | | | | | device tree. Make sure the RB_GOODRANDOM flag only gets set if we read a non-stale /etc/random.seed and we actually filled an .openbsd.randomdata segment.
* Fix definition of KIOC_GETBOOTDUID ioctl.kettenis2020-07-171-2/+2
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* Add a pseudo-driver to "kexec" an OpenBSD/powerpc64 kernel. Heavilykettenis2020-07-162-0/+44
| | | | | based on the octboot driver that we use for octeon. To be used in the bootloader kernel.
* powerpc64 has the sysctl's for power control, so it can use thederaadt2020-07-151-0/+122
| | | | | apmd/apm combo for -L/-H and such. (it gets all the rest of the mess too) ok kettenis
* Add a forward declaration of struct cpu_info.kettenis2020-07-151-1/+3
| | | | Fixes build of RAMDISK kernels.
* Add FDT interrupt support.kettenis2020-07-141-1/+19
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* Mark unmanaged kernel mappings as wired and skip them if we need to evictkettenis2020-07-141-2/+2
| | | | a mapping from the page tables.
* Fix TIB/TCB on powerpc64. Some bright sould decided that the TCB shouldkettenis2020-07-141-2/+2
| | | | | | | | | | | be 8 bytes in the 64-bit ABI just like in the 32-bit ABI. But that means there is no "spare" word in the TCB that we can use to store a pointer to our struct pthread. So we have to treat powerpc64 special. Also recognize that the thread pointer points 0x7000 bytes after the TCB. Since the TCB is 8 bytes this means that TCB_OFFSET should be 0x7008. Pointed out by guenther@; ok deraadt@
* Implement ptrace(2) bits. Still largely untested.kettenis2020-07-141-3/+3
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* Clean up <machine/signal.h>, moving the trapframe struct intokettenis2020-07-132-26/+35
| | | | <machine/frame.h>.
* Implement a machdep.altivec sysctl that always returns 1. This makeskettenis2020-07-111-2/+11
| | | | | | pixman in xenocara build and hopefully helps with ports as well. suggested by matthieu@
* Add hw.cpuspeed and hw.setperfgkoehler2020-07-101-1/+15
| | | | | | | | | Get the list of Pstates from OPAL, and use special registers to request a Pstate or check the current Pstate. The turbo Pstates are higher than the cpu's nominal speed, but the OCC's firmware should throttle down the cpu if it would overheat. ok kettenis@
* Add OPAL_REINIT_CPUS.kettenis2020-07-101-1/+10
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* Add opalsens(4), a driver for sensors provided by the OPAL firmware.kettenis2020-07-071-1/+11
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