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path: root/sys/arch/sgi/include/intr.h (follow)
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* Remove unused spllock().visa2018-08-201-2/+1
| | | | OK deraadt@ mpi@
* Include <sys/mutex.h> instead of <machine/mutex.h>mpi2018-01-221-2/+2
| | | | required by upcoming MI mutex change.
* Define register_splx_handler() in one place.visa2017-06-111-13/+2
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* Let MP-safe interrupt handlers run without the kernel lock on sgi.visa2017-02-111-2/+3
| | | | OK miod@
* Rename mips64's trap_frame into trapframe.mpi2016-03-061-3/+3
| | | | | | For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@
* Add IPI logic. Assign two additional interrupts for inter-processorvisa2015-12-251-1/+3
| | | | | | signalling as a workaround to a limitation in the hub interrupt code, to allow four CPUs per node. At the moment, multi-node setups are not supported.
* intr_barrier(9) for loongson, octeon and sgi.kettenis2015-09-131-1/+3
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* unify the mutex implementations on all the mips64 platforms.dlg2015-07-081-1/+3
| | | | | | | | this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
* Add a dummy IPL_MPSAFE definition.kettenis2013-05-171-1/+4
| | | | ok miod@, mikeb@
* Convert netisr to a normal soft interrupt instead of hanving MD codeclaudio2010-12-211-6/+1
| | | | | | for it. This makes the netisr a real C function which will help further development. No noticable performance change on i386 and amd64. With input from kettenis@ and miod@ additional OKs mikeb@ and henning@
* Define IPL_SCHED as IPL_CLOCK, not IPL_HIGH.miod2010-01-181-3/+4
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* MP-safe pmap implemented, enable IPI in interrupt handler to avoid deadlock.syuu2009-12-281-1/+9
| | | | ok miod@
* IPL_IPI priority raised to IPL_IPI > IPL_HIGH for handling TLB shootdown.syuu2009-12-021-3/+3
| | | | ok miod@
* Now IPI can interrupt to clock interrupt handler.syuu2009-11-261-2/+3
| | | | | It prevents deadlock with TLB shootdown and clock interrupt. ok miod@
* IP30 IPI implementation.syuu2009-11-251-3/+4
| | | | | Also few xheart modification for SMP. ok miod@
* Allow xbow_intr_establish() callers to provide optional storage for themiod2009-11-251-1/+3
| | | | struct intrhand, instead of having it malloc()'ed.
* Get rid of unused `frame' member of struct intrhand; only hardclock() needsmiod2009-10-261-2/+1
| | | | a frame and clock interrupt doesn't need a struct intrhand.
* Completely overhaul interrupt handling on sgi. Cpu state now only stores amiod2009-10-221-59/+46
| | | | | | | | | | | | | | | | logical IPL level, and per-platform (IP27/IP30/IP32) code will from the necessary hardware mask registers. This allows the use of more than one interrupt mask register. Also, the generic (platform independent) interrupt code shrinks a lot, and the actual interrupt handler chains and masking information is now per-platform private data. Interrupt dispatching is generated from a template; more routines will be added to the template to reduce platform-specific changes and share as much code as possible. Tested on IP27, IP30, IP32 and IP35.
* The recent cleanups make blatantly visible that the pending_int handlermiod2009-10-221-5/+5
| | | | | | | | does almost exactly what splx() is doing if ipending is zero, and triggers soft interrupts as well. So don't bother checking for ipending in splx, and always invoke pending_int, which gets renamed as splx_handler for consistency.
* unifdef -DIMASK_EXTERNAL to the mips code. Support for interrupt masking atmiod2009-10-221-30/+9
| | | | | | coprocessor 0 sr level might come back in the future if hardware support requires it, but at the moment it's getting in the way of larger changes. ``In the Attic, noone can hear you scream''
* Replace intrmask_t with uint32_t. This types only describes interrupt masksmiod2009-10-221-13/+8
| | | | | | in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and may be completely alien to real hardware interrupt masks, so don't make things unnecessary confusing.
* Replace IP32 hw_setintrmask() .S routine with a two line C routine.miod2009-10-211-2/+1
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* ipending, cpl moved into cpu_infosyuu2009-10-071-4/+1
| | | | OK miod@
* cpu status flag, cpuid added to cpu_info.syuu2009-09-151-1/+2
| | | | | | cpu_info pointer array, cpu_info iterator, cpu_number() implementation added. constraint modifier fixed in lock.h to output correct assembly. calling proc_trampoline_mp in exception.S.
* Constify the what/name parameter of pci_intr_establish().mk2009-08-221-2/+2
| | | | | | | | | Tested by myself, sthen, oga, kettenis, and jasper. Input from sthen and jasper. ok kettenis (Manpage follows shortly.)
* Make sure splsoftnet() masks softclock; fallout form switch to genericmiod2009-06-121-3/+6
| | | | soft interrupts.
* Switch sgi to per-process AST, and move ast() from interrupt.c to trap.cmiod2009-06-101-2/+1
| | | | where it can use userret() instead of duplicating it.
* Drop almost unused <machine/psl.h> on sgi; move USERMODE() definition frommiod2009-05-221-1/+2
| | | | | | there to trap.c which is its only user. This also cleans up multiple inclusion of <machine/cpu.h> (because <machine/psl.h> includes it) in many places.
* Make sure splx() reenables hardware interrupt sources, even there aren'tmiod2009-05-211-45/+6
| | | | any such interrupts marked as pending.
* Switch sgi to __HAVE_GENERIC_SOFT_INTERRUPTS.miod2009-03-201-39/+61
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* Introduce splsoftassert(), similar to splassert() but for soft interruptmiod2009-03-151-1/+2
| | | | | | levels. This will allow for platforms where soft interrupt levels do not map to real hardware interrupt levels to have soft ipl values overlapping hard ipl values without breaking spl asserts.
* Fix typos/grammatical error in comments.jsing2007-12-061-4/+4
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* registred -> registeredmiod2007-10-141-2/+2
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* Make sure IPL_CLOCK blocks device interrupts.miod2007-06-201-8/+8
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* Move sgo to __HAVE_CPUINFO.kettenis2007-05-071-1/+2
| | | | ok miod@
* Real atomic_{set,clear}bits_int implementation, and replace similarmiod2007-03-231-27/+5
| | | | | {set,clr}_ipending with the above routines. ok kettenis@
* I don't think we're talking about animals in here, somk2006-07-091-3/+3
| | | | s/wether/whether/g.
* remove splimp.brad2006-03-121-3/+1
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* nothing uses spllowersoftclock() anymoremickey2005-04-191-2/+1
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* Un-__P.grange2005-01-311-2/+2
| | | | ok pefo@
* Add IPL_AUDIO/splaudio().kettenis2005-01-021-1/+3
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* Fix some 64 bit address problems.pefo2004-10-201-2/+3
| | | | | Some function names made more unique. Other changes for the upcoming Origin 200 support.
* Rewrite parts of the interrupt system to achive:pefo2004-09-271-18/+19
| | | | | | | | o Remove do_pending code and take a real int instead. The performance impact seems to be very low and it simplifies the code considerably. o Allow interrupt nesting at first level. Run softints with HW ints enabled.
* new style interrupt counters; pefo okderaadt2004-09-241-2/+4
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* Nuke commons.miod2004-09-211-13/+10
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* // is not valid in asm. doh...pefo2004-09-201-2/+2
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* splraise can be inlined or not by definepefo2004-09-201-1/+3
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* Add support for R10K cpu classpefo2004-09-201-2/+6
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* spacingderaadt2004-08-101-17/+17
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* spacingderaadt2004-08-101-3/+3
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