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* unify the mutex implementations on all the mips64 platforms.dlg2015-07-081-72/+2
| | | | | | | | this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
* rework sgi mutexes to use the owner pointer as the lock.dlg2015-04-211-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | this is like src/sys/arch/alpha/alpha/mutex.c r1.14. this changes sgi mutexes so they record which cpu owns the lock rather than just if the lock is held or not. the diagnostics compare the owner to the current cpus curcpu() address so they can actually tell if the current cpu holds the lock instead of whether any cpu holds the lock. instead of using custom asm to implement a cas this uses atomic_cas_ptr. while im here i also shuffled the code. on MULTIPROCESSOR systems instead of duplicating code between mtx_enter and mtx_enter_try, mtx_enter simply loops on mtx_enter_try until it succeeds. this also provides an alternative implementation of mutexes on !MULTIPROCESSOR systems that avoids interlocking opcodes. mutexes wont contend on UP boxes, theyre basically wrappers around spls. we can just do the splraise, stash the owner as a guard value for DIAGNOSTIC and return. similarly, mtx_enter_try on UP will never fail, so we can just call mtx_enter and return 1. tested by and ok miod@
* To prevent lock ordering problems with the kernel lock, we need to make surekettenis2014-02-101-3/+18
| | | | | | | | | | | we block all interrupts that can grab the kernel lock. The simplest way to achieve this is to make sure mutexes always raise the ipl to the highest level that has interrupts that grab the kernel lock. This will allow us to have "mpsafe" interrupt handlers at lower priority levels. No change for non-MULTIPROCESSOR kernels. ok miod@
* MP-safe pmap implemented, enable IPI in interrupt handler to avoid deadlock.syuu2009-12-281-4/+1
| | | | ok miod@
* MP safe mutex.syuu2009-11-041-1/+2
| | | | ok miod@
* Completely overhaul interrupt handling on sgi. Cpu state now only stores amiod2009-10-221-3/+3
| | | | | | | | | | | | | | | | logical IPL level, and per-platform (IP27/IP30/IP32) code will from the necessary hardware mask registers. This allows the use of more than one interrupt mask register. Also, the generic (platform independent) interrupt code shrinks a lot, and the actual interrupt handler chains and masking information is now per-platform private data. Interrupt dispatching is generated from a template; more routines will be added to the template to reduce platform-specific changes and share as much code as possible. Tested on IP27, IP30, IP32 and IP35.
* Oops, IPL_NONE is not zero in HEAD.miod2007-05-141-2/+2
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* Define MUTEX_OLDIPL where they were missing, will be used (reasonably) shortly.miod2007-05-051-1/+3
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* Simple monoprocessor mutex implementation, faster than the MI code, four leftmiod2007-05-011-0/+59
to go.
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