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path: root/sys/arch/sgi/pci/macepcibridge.c (follow)
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* Remove the unused interrupt type (edge/level) from the mace interruptvisa2018-12-031-3/+3
| | | | | | | | handler registration. The code is inherited from isa(4), but on the O2, although some interrupt sources on CRIME are edge-triggered, all the MACE interrupts are level-triggered. From miod@
* The device_to_pa routine really isn't needed. We always have physicalvisa2017-05-111-16/+3
| | | | | | | addresses. While there, pave the way for BUS_DMA_64BIT (not working yet). Diff from miod@; OK dlg@
* Format string fixes and removal of -Wno-format for sgi. Based upon anmiod2014-05-191-5/+3
| | | | initial diff from jasper@
* Moar <uvm/uvm.h> -> <uvm/uvm_extern.h> love.mpi2014-04-031-2/+1
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* Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofmiod2012-09-291-2/+2
| | | | such statements with it.
* No longer allow bus_space_barrier() to be a NULL pointer on a givenmiod2012-03-151-5/+12
| | | | | bus_space_tag on sgi, but rather always provide at least a dummy asm("sync") flavour. Saves a function pointer test at runtime.
* Extend pci_probe_device_hook() on sgi xbridge(4) to return either the straightmiod2011-10-101-21/+25
| | | | | | | | | | | accessors or the byte-swapped accessors, depending upon the byteswap setting of the device we are trying to attach. This allows for the removal of byteswap knowledge from ioc(4) and iof(4) drivers. While there, build pci_chipset_t md structs by bcopy'ing a template and filling the few runtime fields, instead of assigning every field of them.
* Introduce pci_probe_device_hook(pci_chipset_tag_t, struct pci_attach_args *).miod2011-10-101-1/+9
| | | | | | | | | | | | | | | | | | This mandatory function will get invoked in pci_probe_device(), and allows a pci host driver to alter the pci_attach_args passed to a device when attaching. This function will also, if returning non-zero, cause the device to be skipped completely during all the phases of the PCI device discovery (i.e. ressource enumeration, ressource assignment, and actual attachment). This particular feature is experimental and might be reverted in the future (or the scope narrowed to device attachment only). A dummy #define pci_probe_device_hook() 0 is added to all platforms except sgi, where real functions (currently only returning 0) are added; real meat will be added shortly. Discussed at s2k11, no objection from the usual suspects.
* Introduce a new pci routine, pci_conf_size(), which returns the size of amiod2010-12-041-1/+9
| | | | | | | given pcitag_t configuration address space. Currently, all pci controllers will return the usual 0x100 bytes of PCI configuration space, but this will eventually change on PCIe-capable controlers. ok kettenis@
* remove unused offset argument to rbus functionsjsg2010-09-221-3/+3
| | | | ok krw@ kettenis@
* Implement bus_space_barrier() on sgi; on xbridge, this will also flushmiod2010-08-231-3/+5
| | | | the pci write buffers.
* Obtain struct sgi_device_location for the console input and output devices,miod2010-04-061-7/+15
| | | | | and compare against them when attaching potential console drivers, to figure out whether they indeed are acting are console devices or not.
* Add an MD interface for PCI drivers to be able to retrieve the node and widgetmiod2010-03-071-1/+17
| | | | | number the PCI bus they are on is connected to. Will be used shortly to help the console device selection logic.
* Better crime/mace interrupt handling; interrupt information is no longermiod2009-10-261-20/+17
| | | | | | | | specified in the kernel configuration file, but is provided by macebus(4) as part of the child device attachment args, and provide both crime and mace interrupt bitmasks; this allows us to only really enable interrupt sources we care about, and to avoid invoking interrupt handler we don't need to for the few mace interrupts multiplexed at the crime level.
* Implement bus_space_vaddr() for macepcibr.miod2009-10-221-1/+10
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* Make macebus_intr_disestablish() signature sane, and update its caller.miod2009-10-221-3/+3
| | | | Still unimplemented for now.
* Constify the what/name parameter of pci_intr_establish().mk2009-08-221-3/+3
| | | | | | | | | Tested by myself, sthen, oga, kettenis, and jasper. Input from sthen and jasper. ok kettenis (Manpage follows shortly.)
* typo; bradmiod2009-08-091-2/+2
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* Clear the upper part of 64 bit memory BARs, for they show up as 0xffffffffmiod2009-08-091-7/+9
| | | | otherwise. Found the hard way by jasper@, playing with a bge card.
* Don't forget to bus_space_unmap(), even if it's a no-op, in rbus_space_unmap().miod2009-07-261-1/+2
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* Get rid of now unused extent_malloc_ok variable.miod2009-07-221-3/+1
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* Get rid of bus_space_tag_t now unused bus_extent and bus_reverse fields.miod2009-07-221-12/+3
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* Overhaul resource handling and mapping in macepcibr(4):miod2009-07-221-109/+71
| | | | | | | | | | | | - do not use a stinking extent to track bus_space_map allocations, but directly map in XKPHYS instead. What are 64 bit address spaces good for if we still need to use TLB for that? - provide proper resource management extents to the MI pci code, so that, in turn, the cardbus code can reuse them instead of providing their own. - use the whole 4GB address space window for PCI I/O resources, just because we can. - make sure no device can get assigned address zero in I/O space, because this address triggers a PCI error.
* PCI-Cardbus bridge support for both O2 (macepcibr) and Octane/Origin (xbridge)miod2009-07-211-28/+134
| | | | | | | | | | class systems. Tested on O2 and Origin 200 with wi@pcmcia and xl@cardbus, using a Ricoh 5C475-based cbb(4) board. acx@cardbus doesn't work reliably yet, so your mileage may vary until more bugs are fixed. Thanks to matthieu@ for lending me some cardbus devices for testing.
* Simplify code that sanitizes pci resources on the O2's mace PCI bridge.kettenis2009-07-191-10/+75
| | | | | | | The firmware messes up I/O BARs, so whack those back to 0, such that the MI PCI code initializes on an as-needed basis. ok miod@
* Update bus_dma to the better codebase found on almost all other platforms,miod2009-07-171-1/+2
| | | | | | | | | | where the common part to all bus_dmamap_load*() functions is implemented in in an internal load_buffer routine. This allows the xbridge-specific dma code to only provide this function, instead of three; and this also brings us a working bus_dmamap_load_uio() on all supported sgi machines, which in turns make crpyto(4) devices really work. Tested with hifn(4).
* Make the PCI-PCI bridge initialization code bus-independent, relying on amiod2009-07-161-83/+156
| | | | | | | per-pci_chipset_t function to perform actual resource allocation. Add the necessary bits to macepcibr(4), and enable ppb(4) on O2 kernels now. Joint effort with kettenis@
* Cheat in pci_conf_read() and force the REXTVALID bit in the O2 onboard ahc(4)miod2009-07-161-5/+11
| | | | | | configuration register; this allows the driver to select ultra speed, which this particular hardware supports. From Linux, ok kettenis@
* Extend PCI mmio address space by using a bigger window that requires 64-bitkettenis2009-04-251-2/+3
| | | | | | adressing (no problem since we only support 64-bit mode). ok miod@, jsing@
* Fix interrupt mapping for devices behind PCI-PCI bridges.kettenis2009-04-191-11/+17
| | | | ok miod@
* Attach pci busses with pba_bus being zero, and not our bridge unit number,miod2009-04-181-2/+2
| | | | | these are completely unrelated as long as there is only one pci bus per bridge.
* bzero pci attach argskettenis2009-03-301-2/+2
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* Implement bus_space_{read,write}_raw_mult_[248] correctly, it needsmiod2008-07-301-1/+79
| | | | | endianness conversion on pci bridges. ok deraadt@ jsing@
* Proper interrupt values for pci interrupt pins B to D, found in some IRIXmiod2008-07-301-19/+18
| | | | developer documentation some time ago.
* Completely overhault attachment rules on sgi. No more indirect configurationmiod2008-02-201-2/+2
| | | | | | | | inherited from OpenBSD/arc machines with ISA bus; mainbus children match on device name and other hierarchies match on simplified locators. As a bonus, attachment lines in dmesg will now print their locators. ok jsing@
* Remove unused fields of struct mips_pci_chipset.miod2008-02-161-2/+1
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* No need to include <machine/pte.h> here.miod2007-10-181-2/+1
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* Extent sgi bus_dma to cope with different views of memory: non-contiguousmiod2007-06-211-3/+29
| | | | | | | for the cpu, contiguous from different bases for devices. This allows memory above 256MB to be used with bus_dma (and we had really been lucky with the first few large-memory builds). Information about memory accesses taken from Linux.
* Make pci subsystem aware of domains. Each host bridge gets assigned a uniquekettenis2006-12-141-1/+2
| | | | | | | | domain number such that we can distinguish between busses with the same bus number that are behind different host bridges. Domains can be accessed by using different device nodes. ok deraadt@
* * Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set tobrad2006-03-131-1/+2
| | | | | | | | | | NULL for root PCI busses. For busses behind a bridge, it points to a persistent copy of the bridge's pcitag_t. This can be very useful for machine-dependent PCI bus enumeration code. From NetBSD ok grange@ kettenis@
* Stop abusing phys_map to know if it is safe to use malloc in extent routines;miod2006-01-041-12/+8
| | | | | instead use a global flag, like some other architectures do. No functional change.
* Do not return zero in bus_space_map() on failure (sigh).miod2006-01-041-2/+3
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* Un-__P.grange2005-01-311-3/+3
| | | | ok pefo@
* Fix some 64 bit address problems.pefo2004-10-201-76/+76
| | | | | Some function names made more unique. Other changes for the upcoming Origin 200 support.
* new style interrupt counters; pefo okderaadt2004-09-241-2/+2
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* Add support for R10K cpu classpefo2004-09-201-2/+2
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* various ansi and spacing issues; pefo okderaadt2004-08-111-2/+2
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* spacingderaadt2004-08-101-21/+21
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* initial sgi importpefo2004-08-061-0/+566
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