wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	When computing the total resources required by devices behind a ppb, take	miod	2009-07-23	1	-3/+20
\| \| \| \|	PCI ROM into account, if any.
*	PCI-Cardbus bridge support for both O2 (macepcibr) and Octane/Origin (xbridge)	miod	2009-07-21	1	-4/+30
\| \| \| \| \| \| \| \| \| \|	class systems. Tested on O2 and Origin 200 with wi@pcmcia and xl@cardbus, using a Ricoh 5C475-based cbb(4) board. acx@cardbus doesn't work reliably yet, so your mileage may vary until more bugs are fixed. Thanks to matthieu@ for lending me some cardbus devices for testing.
*	Program PPB_REG_PREFLIM_HI32, not PPB_REG_PREFBASE_HI32 a second time. Oops.	miod	2009-07-16	1	-2/+2
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*	Make the PCI-PCI bridge initialization code bus-independent, relying on a	miod	2009-07-16	1	-13/+203
\| \| \| \| \| \| \|	per-pci_chipset_t function to perform actual resource allocation. Add the necessary bits to macepcibr(4), and enable ppb(4) on O2 kernels now. Joint effort with kettenis@
*	Extend xbridge to support shared interrupt handlers, and perform PCI-PCI	miod	2009-07-13	1	-0/+50
	bridge initialization if necessary; enable ppb on IP27 and IP30 kernels. With feedback from kettenis@; macepcibr to gain the same functionality soon.