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* simplify pckbc_xt_translation()shadchin2012-08-102-6/+6
| | | | | | | | * call only for set translation on (once in /sys/dev/pckbd.c) therefore we can delete unused code. * change behavior (more standard) - return zero on success ok miod@
* Attach non-frame buffer GIO devices with ga_product being the id gathered bymiod2012-07-181-3/+4
| | | | | gio_id(), not the whole 32 bit first word. Some boards with a 8-bit only ID register use the other 24 bits, sadly.
* Hopefully correctly recognize GIO boards with a 8-bit only ID register, whichmiod2012-07-181-4/+13
| | | | are not frame buffers. Thanks to Martin Boehme for donating such boards!
* regenmiod2012-07-182-8/+12
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* A couple more device IDs, thanks to Martin Boehme for donating boards!miod2012-07-181-4/+6
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* According to Linux, and just verified the hard way, the 8254 timer does notmiod2012-07-184-5/+17
| | | | | | | | | interrupt on Indy; do not use it on such systems. Then, bring back a clock0 at mainbus attachment to IP22 kernels, and attach it late in the autoconf process if no other device has claimed the clock yet. This means R4000 and R4400 based Indy may experience the lost clock interrupt processor errata again, until a better way to skirt it is found.
* Forgot these files during the recent clock churning.miod2012-07-161-2/+2
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* A known errata of R4000 and R4400 processors, is that reading the internalmiod2012-07-146-20/+85
| | | | | | | | | | | | counter register close to a trigger of the counter interrupt, may cause the interrupt not to be generated. This makes it a bad idea to use the internal counter both for the scheduling clock and for delay(). Therefore, on IP22 systems (and IP28 because it makes my life easier), use one of the two 8254 timers connected to the onboard interrupt controller as the scheduling clock source. Adapted from NetBSD.
* Correctly register contiguous memory regions which start within the ARCBiosmiod2012-06-281-3/+12
| | | | | | | | | | | | | reported memory but end beyond it, such as > 1GB DIMMs in bank 0. Also, currently restrict physical memory usage to 1.5GB - there seems to be a bogus 32 bit truncation happening in the IP30 specific codepath, which in turns ends up causing the low memory alias region (and thus, the exception vectors and the NMI handler) to be overwritten, which I can't find from code inspection (does anyone has 2GB of Octane memory to spare?) Both issues reported and fix/workaround tested by Florentijn van Kampen, thanks!
* create new machine/_float.h which is namespace clean. create a newderaadt2012-06-263-8/+3
| | | | | | | | | MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
* Code for the external L2 cache controller on Indy/Indigo2 R4600SC and Indymiod2012-06-243-4/+153
| | | | | | | | | | R5000SC processor modules; these sport an up to 512KB, physically indexed, write-through L2 cache which is not connected to the canonical external cache interface of these processors (hence requiring specific code to drive it). The cache is enabled early and disabled before returning to ARCBios (for very nasty things happen otherwise). Tested on R5000SC, will be tested on R4600SC soon.
* Add cache operation functions pointers to struct cpu_info; the variousmiod2012-06-244-62/+22
| | | | | | | | | cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
* Using the LLAddr register to store our curcpu() pointer on R10k SMP kernelsmiod2012-06-175-18/+58
| | | | | | | | | | was a nice trick, but this register is only 32-bit wide and will be sign-extended, which requires all cpu_info structs to be allocated within 2GB physical - something which may not be possible on some configurations. This diff changes IP30.MP kernels to no longer use LLAddr to store curcpu, but use unused fields of the MPConf structure in low memory, indexed with the physical processor id, which can be obtained from the Heart PRID register.
* Correctly compute the IOC3 device mask on MENET boards.miod2012-05-301-2/+2
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* Make it possible to disable the Sync-on-Green signal by setting themikeb2012-05-295-6/+19
| | | | | | | | ARCBios environment variable OSLoadOptions to "nosog". Now everyone can enjoy running O2 without an SGI monitor and don't turn vegetarian afterwards. All the essential bits come from NetBSD's crmfb driver except they've chosen to use a "SyncOnGreen" variable not saved by the ARCS. Pointers and corrections from and ok miod, jsing
* When writing the new volume header to disk, write back the wholematthew2012-05-291-2/+2
| | | | | | | sector rather than just the bytes for the volume header itself. Silences the "sloppy I/O" warnings triggered by sgi's distrib scripts. tested and ok deraadt
* The link state code does not work correctly on Indigo (IP20) and E++ GIO boardsmiod2012-05-282-4/+9
| | | | | | | | | and will report the link being down too aggressively. Better to always report the link as up - these systems and boards are single media only so it won't harm much. Unbreaks dhcp in the installer on these interfaces; found the hard way by sebastia@
* Add a `L2 cache line size' member to struct cpu_info. This allows R4k code tomiod2012-05-271-3/+2
| | | | | | stop abusing another field, and will be used by more routines RSN. No functional change.
* Proper support for the so-called `fast mode' of the Indigo2 ECC memorymiod2012-05-2710-55/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | controller. In this mode, access to physical memory are not allowed to bypass the cache, and this allows the memory subsystem to run faster. Of course, some device drivers will require uncached memory access (e.g. for proper HPC DMA descriptor operation). New ip22-specific functions to switch between `fast mode' and `slow mode' are introduced. hpc(4) now provides read and write routines to fetch a dma descriptor from uncached memory into a local copy, and update it from said modified copy. On systems without the ECC MC, these will do nothing and operation will continue to access the uncached memory directly. On systems with the ECC MC, they will perform a copy, and the writeback will be done in slow mode. bus_dmamem_map() requests for DMA memory with BUS_DMA_COHERENT set in flags, which would return uncached memory, will now always fail on systems with the ECC memory controller. Drivers which really need uncached memory, and are aware of this particular setup, will now pass BUS_DMA_COHERENT | BUS_DMA_BUS1, which will let the request succeed. sq(4) will use all of the above to work mostly unmodified on ECC MC systems in fast mode. Finally, fast mode is enabled after autoconf. Tested on IP22 and IP28.
* Decide once for all whether IP22/IP28 systems are running with the ECC memorymiod2012-05-273-46/+62
| | | | | | | controller or not, and store this in a global variable. This is better than checking for the IP number everytime, especially since, according to IRIX header files, not all IP26 use the ECC memory controller (not that it matters much for us since we do not run on them yet)
* Be more strict when specifying hpc child device attachments: specificmiod2012-05-264-20/+16
| | | | | | onboard devices need only attach to hpc0 instead of hpc?. While there, remove hpc1 and hpc2 attachment from IP28 configurations, as these can not exist on Indigo2 systems.
* On IP28, silently acknowledge bus errors which can be attributed tomiod2012-05-252-10/+39
| | | | | | | speculative execution, while in kernel mode, attempting to access bogus physical address through CKSEG[01] or XKPHYS. Surprisingly enough, an IP28 system can boot multiuser without triggering any such error; they will only show up if there is a lot of I/O (and thus, context switching).
* Support for the POWER Indigo2 R10000 systems (IP28). Currently running withmiod2012-05-258-15/+251
| | | | | ECC checking disabled, which allows the existing Indigo2 drivers to run unmodified.
* Make the multicast filter routine conform to the Party's standards. Adaptedmiod2012-05-221-29/+26
| | | | from a (non-compiling) diff from Brad.
* When setting up the multicast filter, use the ac_multicnt field of the arpcommiod2012-05-222-7/+7
| | | | | struct to know if there are multicast entries, instead of counting the number of entries in the list. No functional change. From brad.
* Make sure the generic bus_dmamem_alloc() routine restricts its allocation tomiod2012-05-202-185/+11
| | | | | | the dma_constraint range. This allows the xbridge(4) bus_dma_tag_t to use the generic routines instead of rolling its own, now that the ATE code has been removed.
* Port NetBSD's pci@gio driver for fast Ethernet expansion boards for themiod2012-05-183-2/+512
| | | | | | IP22 family. This is just the bridge so far, as the underlying pci drivers will need some changes to work (dc(4) does not work correctly yet, and tl(4) needs to be bus_dma'ified).
* Yet another rework of the crucial gio_id() function responsible for correctlymiod2012-05-172-65/+33
| | | | | | | | | | | | | | | | | recognizing a GIO device or an id-less frame buffer in a GIO slot. Turns out that GIO32 devices (at least those with a 32-bit ID register, but likely all of them) do NOT like accesses to the minimal GIO register area NOT done on 32-bit boundaries. While frame buffers won't mind, especially if their slots are pipelined. This makes it a lot easier to tell them apart. While there, split gio_intr_establish() into gio_intr_map(), which will return a logical interrupt number out of a GIO slot number, and gio_intr_establish(), which will now expect a logical interrupt number, instead of a logical slot number. These two functions are still unused, but upcoming changes depend on this work. (Yes, I'm too lazy to make two commits for this tonite)
* Better probes for sq and wdsc in gio-masqueraded-as-hpc expansion boards.miod2012-05-171-11/+54
| | | | | Previous change was a tad too optimistic. This repairs E++ and GIO SCSI board operation.
* revert a chunk introduced in 1.7 which was not supposed to be there yetmiod2012-05-151-2/+3
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* Don't forget to print the frame buffer name obtained from ARCS, as all othermiod2012-05-121-2/+6
| | | | GIO frame buffer drivers do.
* Strip trailing space from ARCS frame buffer names.miod2012-05-121-3/+7
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* It turns out that, when the IRIX header files mention CTR/DCD/DTR/RTS wiringmiod2012-05-122-21/+22
| | | | | | | | | | | | | | | is inverted on Indigo, this just means that Indigo does not use the same values as the later models. It does not mean that the Indigo is using wrong values, which is how I first read this. In reality, Indigo systems use the expected values of these signals being active low, while later designs use active high signals. So yes, some systems have inverted values - but the ones which need compensating are not those I thought. Change the logic to do TRT, but keep the device flags check, to be able to force the other behaviour if the kernel guesses wrongly. Tested on Indigo, Indy and Indigo 2.
* GIO devices with a 32-bit device identifier actually do not like halfword andmiod2012-05-102-24/+48
| | | | | | | | | | | | | | byte accesses to the ID register; instead of interpreting this is as a lack of hardware, reconize this as a valid GIO device (if the `has a 32-bit ID' bit is set, that is). This allows GIO Impact boards, which use a 32-bit ID, to be recognized correctly, and to work as a console device. Commited from an Indigo2 with glass console on the single-board Impact (MG10) board which arrived in the mail today. Would have been done even earlier, had I not forgotten to connect the extra power supply cable to the Impact GIO backplane...
* regenmiod2012-05-102-8/+9
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* Do not keep the `32-bit device ID' bit indicator in the device IDs, formiod2012-05-101-6/+9
| | | | consistency. Will be necessary shortly.
* Fix a few macros to operate on the right bit.miod2012-05-101-3/+3
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* Fix impact(4) header file generation to correctly output NIMPACT_GIO onmiod2012-05-103-8/+8
| | | | IP22 kernels. Oops.
* Be more strict in the `are we the console device' logic at device attachmentmiod2012-05-104-8/+25
| | | | | time; not only do we need to match the graphics console address, but cn_tab needs to point to wsdisplay, too.
* Initialize more proc0 context before invoking consinit(); this now reallymiod2012-05-101-4/+9
| | | | allows probes to fault and correctly recover.
* Update the depencies of the .S files on assym.h; allows IP30 kernels to be builtmiod2012-05-061-3/+3
| | | | with -j2.
* sq needs ifmedia attribute now, repairs RAMDISK_IP22miod2012-05-021-2/+2
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* Add ifmedia support to sq(4).miod2012-04-303-17/+234
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* Pass the base address of the hpc to child devices, to let them be able tomiod2012-04-302-12/+14
| | | | | figure out whether they attach to the onboard hpc or to an expansion slot (or the Challenge S IO+ mezzanine). No functional change (yet)
* Correctly read board version information.miod2012-04-302-9/+10
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* Recognize 85230 chips, and take advantage of their FIFOs to reduce themiod2012-04-295-49/+107
| | | | amount of TX empty interrupts.
* I am not sure what the mess with the wiring of carrier lines on Indigo resolvesmiod2012-04-292-5/+12
| | | | | to, so make this controllable with device flags, and default to non-bogus wiring.
* Be sure to initialize the `state' member of the softc when attaching themiod2012-04-281-9/+5
| | | | | console keyboard, otherwise led update commands will never get transmitted. Noticed by sebastia@
* Only trust giofb_consid if non-zero.miod2012-04-281-2/+2
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* Fix the `all keys up' event handling logic to only apply to it, and not tomiod2012-04-271-2/+2
| | | | | regular `one key is up' events. Makes the shift, alt, ctrl, etc keys behave as expected after the next keystroke.
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