| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | The minimum frame size for the ELFv2 ABI is 32 bytes. Using this value |   kettenis | 2020-06-22 | 3 | -87/+86 |
| | | | | | | | | instead of 48 in the trap setup functions makes it possible to get rid of the magic offset in proc_trampoline. Suggested by gkoehler@ | ||||
| * | Enable interrupts when they were enabled before the trap (except when we | kettenis | 2020-06-22 | 1 | -7/+4 |
| | | | | | | are handling "genuine" interrupts like the decrementer and hypervisor virtualization interrupts). | ||||
| * | Handle data storage and data segment interrupts from userland as well. | kettenis | 2020-06-22 | 3 | -18/+66 |
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| * | Make return-to-user and kernel re-entry work. This adds a per-pmap SLB | kettenis | 2020-06-22 | 9 | -14/+105 |
| | | | | | | | cache. We might want to turn that in a per-proc cache at some point, but this gets us to the point where we can sucessfully have init(1) do its first system call. | ||||
| * | Fix previous commit; pasted instructed in the wrong spot. | kettenis | 2020-06-22 | 1 | -2/+2 |
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| * | Add magic offset to make the frames line up. | kettenis | 2020-06-22 | 1 | -1/+2 |
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| * | Implement setregs(). | kettenis | 2020-06-22 | 1 | -2/+9 |
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| * | Provide working definitions of PROC_STACK() and PROC_PC(). | kettenis | 2020-06-22 | 1 | -3/+3 |
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| * | Change tsc_get_timecount return from uint to u_int per sys/timetc.h. |   pirofti | 2020-06-22 | 1 | -3/+3 |
| | | | | | First brought up by naddy@ in the usertc thread, OK kettenis@. | ||||
| * | enable nvme on i386. |   dlg | 2020-06-22 | 2 | -2/+5 |
| | | | | | ok deraadt@ | ||||
| * | Making tracing through traps work. | kettenis | 2020-06-21 | 1 | -2/+19 |
| | | | | | ok gkoehler@ | ||||
| * | Enable machine check interrupt. | kettenis | 2020-06-21 | 1 | -2/+2 |
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| * | Set PTE valid bit in PTE descriptors such that we actually match them in | kettenis | 2020-06-21 | 1 | -4/+2 |
| | | | | | pmap_ptedinhash(). | ||||
| * | Set reference count of freshly created pmap to one. | kettenis | 2020-06-21 | 1 | -1/+2 |
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| * | Set up exec_map and phys_map. | kettenis | 2020-06-21 | 2 | -3/+23 |
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| * | Add code to synchronize I-cache if necessary when mapping an executable | kettenis | 2020-06-21 | 1 | -2/+26 |
| | | | | | page. | ||||
| * | Implement copyin(9), copyout(9), copyinstr(9) and copyoutstr(9). | kettenis | 2020-06-21 | 10 | -36/+212 |
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| * | Add bcmtmon(4), a driver for the temperature sensor on the Raspberry Pi 4. | kettenis | 2020-06-20 | 1 | -1/+2 |
| | | | | | Written by Alastair Poole. | ||||
| * | VM_MAXUSER_ADDRESS needs to be page-aligned. | kettenis | 2020-06-19 | 1 | -1/+1 |
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| * | Fix calculation of the year. | kettenis | 2020-06-19 | 1 | -2/+2 |
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| * | Not quite correct implementations of copystr(9) and kcopy(9). | kettenis | 2020-06-19 | 1 | -7/+20 |
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| * | First stab at implementing system calls. | kettenis | 2020-06-19 | 2 | -2/+109 |
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| * | Set %r13 with a pointer to our per-CPU info struct when setting up a | kettenis | 2020-06-19 | 1 | -1/+2 |
| | | | | | trapframe. | ||||
| * | fold the TSC value in fewer operations, same result; ok deraadt@ |   naddy | 2020-06-19 | 2 | -12/+13 |
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| * | AST handling. | kettenis | 2020-06-18 | 3 | -6/+54 |
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| * | Cache kernel SLB entries in per-CPU struct and restore them upon | kettenis | 2020-06-18 | 5 | -25/+74 |
| | | | | | kernel entry. | ||||
| * | Add pcamux(4), a driver for the PCA8548 I2C switch. | kettenis | 2020-06-18 | 1 | -1/+3 |
| | | | | | ok patrick@ | ||||
| * | Enable bwfm(4) on armv7 RAMDISK for SD/MMC and USB devices. |   fcambus | 2020-06-18 | 1 | -1/+3 |
| | | | | | OK patrick@ | ||||
| * | Print CPU name and cache info in the same way as we do on arm64. | kettenis | 2020-06-17 | 2 | -7/+95 |
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| * | More pmap bits, mostly from powerpc andd arm64. | kettenis | 2020-06-17 | 2 | -19/+492 |
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| * | Explicitly unmap DMA memory using pmap_kremove(9). | kettenis | 2020-06-17 | 1 | -1/+2 |
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| * | Attach secondary CPUs early. Since on most machine we need psci(4) to | kettenis | 2020-06-17 | 1 | -4/+21 |
| | | | | | | | | | | spin op the secondary CPUs, explicitly probe and attach that driver before we attach the CPUs. This should help with distributing interrupts across CPUs on arm64. ok patrick@, deraadt@, dlg@ | ||||
| * | add a dumb pci_intr_establish_cpu(). | dlg | 2020-06-17 | 2 | -2/+16 |
| | | | | | | | | | | i386 doesnt support msix, and the interrupt code assumes that it only ties stuff to cpu0. this mostly exists so the api exists for multiq drivers to compile against, but fail with when they try to use it. tested with a hacked up vmx(4). | ||||
| * | pci_intr_establish_cpu() for establishing an interrupt no a specific cpu. | dlg | 2020-06-17 | 6 | -18/+37 |
| | | | | | | | | | | | | | | | | | | | | the cpu is specified by a struct cpu_info *, which should generally come from an intrmap. this is adapted from a diff that patrick@ sent round a few years ago for a pci_intr_map_msix_cpuid, where you asked for an msi vector on a specific cpu, and then called pci_intr_establish with the handle you get. kettenis pointed out that it's hard on some archs to carry cpu on a pci interrupt handle, so i tweaked it to turn it into a pci_intr_establish_cpu instead. jmatthew@ and i (but mostly jmatthew@ to be honest) have been experimenting with this api on multiple archs and it is working out well. i'm putting this diff in now on amd64 so people can kick the tyres a bit. tested with hacked up vmx(4), ix(4), and mcx(4) | ||||
| * | sparc64 should define __HAVE_PCI_MSIX | dlg | 2020-06-17 | 2 | -2/+48 |
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| * | make intr_barrier run sched_barrier on the cpu the interrupt pinned to. | dlg | 2020-06-16 | 1 | -3/+4 |
| | | | | | | | intr_barrier passed NULL to sched_barrier before this, which ends up being the primary cpu. that's been mostly right until this point, but is set to change. | ||||
| * | Some simplifications. | kettenis | 2020-06-16 | 1 | -50/+90 |
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| * | Add missing dependeny. | kettenis | 2020-06-16 | 1 | -2/+2 |
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| * | Check rdrand for success and try up to ten times, as recommended by Intel. | naddy | 2020-06-15 | 2 | -6/+38 |
| | | | | | | Do the same for rdseed. ok deraadt@ | ||||
| * | update powerpc64 include paths for 5.7 drm |   jsg | 2020-06-15 | 1 | -2/+5 |
| | | | | | ok kettenis@ | ||||
| * | Implement cpu_rnd_messybits() as a read of the cycle counter register. | naddy | 2020-06-14 | 2 | -12/+13 |
| | | | | | ok dlg@ deraadt@ | ||||
| * | Implement cpu-rnd_messybits() as a read of the cycle counter register. | kettenis | 2020-06-14 | 2 | -12/+10 |
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| * | Remove debug code. | kettenis | 2020-06-14 | 1 | -6/+1 |
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| * | Enable ahci(4). | kettenis | 2020-06-14 | 1 | -2/+2 |
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| * | Provide address space extents. While the firmware does configure the bridge | kettenis | 2020-06-14 | 1 | -1/+37 |
| | | | | | | | windows it doesn't enable the bus master bit in the command register. This prevents DMA from working. By providing the address space extents ppb(4) will automatically configure the bridge and set the bit. | ||||
| * | Get context switching between kernel threads going. | kettenis | 2020-06-14 | 16 | -48/+225 |
| | | | | | | | Since the stacks for kernel threads are not mapped 1:1 this involves translating virtual addresses into physical addresses when making OPAL calls. | ||||
| * | Put a bit more information in the panic message. | kettenis | 2020-06-14 | 1 | -5/+3 |
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| * | Parse bootargs. | kettenis | 2020-06-14 | 1 | -6/+67 |
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| * | do not need assym.h |   deraadt | 2020-06-14 | 1 | -2/+1 |
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| * | Add -msoft-float, -mno-altivec and -mno-vsx to the compiler flags. | kettenis | 2020-06-14 | 1 | -2/+2 |
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