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* vmm(4): Pass through CPUID function/leaf 0x16 for processor speed.mlarkin2019-06-131-8/+6
| | | | ok deraadt, pd, phessler
* Remove unused scheduler related definitions.mpi2019-06-115-19/+5
| | | | ok visa@
* add mcx now that pyro and sparc64 can do msi-xdlg2019-06-111-1/+2
| | | | ok jmatthew@
* implement msi-x support on sparc64.dlg2019-06-114-20/+126
| | | | | | | | | | | | | | | | | | | | | | | | this is mostly based on the stuff kettenis did on arm64 recently. msix support is basically the same as msi support from the host side, you just have to tell the actual device about the msi vectors differently. the most complicated part of this is storing the requested msix vector between the call to pci_intr_map_msix and pci_intr_establish. the pci_intr_handle_t for storing state between those is a scalar type, so we reassign some bits in that int for use storing the type of int (intx, msi, or msix) and the vector. i took the low 8 bits for storing the vector, which gives us a max of 256 values. technically msix supports up to 2048 vectors, but pyro only supports 256 in total, so i don't think we're going to miss out on much. vpci may support more, but we'll cross that bridge when we get to it. i tested pyro(4) with mcx(4). vpci was tested by kettenis@ ok kettenis@
* Use PWAIT instead of PUSER in tsleep(9).mpi2019-06-101-2/+2
| | | | | | | It doesn't matter in this case and reducing the number of PUSER makes the scheduler logic easier to understand. ok kettenis@, visa@
* Allow memory that isn't (32-bit) DMA reachable when loading a map that waskettenis2019-06-091-3/+5
| | | | | | created with the BUS_DMA_64BIT flag. ok jsg@
* When loading intel microcode in the non-efi case, error if the file isjsg2019-06-084-8/+8
| | | | | | | larger than 256KB not 128KB to cope with the 06-8e-09 microcode which is currently 193KB. Reported and tested by Paul de Weerd. Matches a diff from claudio@
* add ukspan(4), a driver for the Keyspan USA19HS USB serial adapterjcs2019-06-071-1/+3
| | | | written by Cody Cutler <ccutler at csail.mit.edu>
* enable mcx(4) on arm64, found in Packet's g2.large.arm servers.jmatthew2019-06-072-2/+4
| | | | tested by and ok patrick@
* Stop promoting the TSC as a high quality timecounter on MULTIPROCESSORkettenis2019-06-061-1/+5
| | | | | | | | | systems. There is no guarantee that the TSCs on different cores are synchronized when the OpenBSD kernel boots and we don't have code to synchronize them ourselves. This affects both AMD and Intel CPUs and even cores on the same socket can by out of sync. ok deraadt@, sthen@
* Remove the unused pvh_attrs attribute from struct vm_page_md.patrick2019-06-041-4/+2
| | | | ok kettenis@
* Bump MAXCPUS to 32 so that we can use all cores on the Ampere eMAG.patrick2019-06-041-2/+2
| | | | ok kettenis@
* Map the raw bus space operations to the regular ones.patrick2019-06-031-1/+15
| | | | ok kettenis@
* Fix priorities of LIPs to match the other changes made in rev 1.17.kettenis2019-06-031-2/+2
| | | | | | Makes MSI/MSI-X actually work reliably on machines with agintc(4). ok patrick@
* Change pci_intr_handle_t into a struct and replace duplicated code thatkettenis2019-06-024-183/+102
| | | | | | | | implements mapping of MSI and MSI-X interrupts with new generic functions. Fixes a use-after-free in sone PCI device drivers that call pci_intr_string(9) after pci_intr_establish(9). ok deraadt@
* Refactor the MAP_STACK feature, and introduce another similar variation:deraadt2019-06-019-176/+37
| | | | | | | | | Lookup the address that a syscall instruction is executed from, and kill the process if that page is writeable. This brings an aspect of W^X behaviour to W|X mappings (in JITs not yet adapted to W^X). The goal is to remove simple attack methods and force use of ret2libc or other more complicated means. ok kettenis stefan visa
* Bump VM_MAX_KERNEL_ADDRESS so that we have about 16G of KVA. Sincepatrick2019-06-011-2/+2
| | | | | | | | | we need KVA to keep track of all the RAM pages, machines with a lot of memory easily exhaust our KVA space. We need about 1G of KVA per 32G of memory, so with 16G of KVA we can maintain close to 512G of memory. ok kettenis@
* On machines with large amounts of physical memory we fail to initialize uvmkettenis2019-06-012-13/+66
| | | | | | | | | | because we don't have enough kernel memory available in the early bootstrap phase to allocate the vm_page structures. Fix this by making uvm_growkernel() work before uvm is initialized like we do on other architectures that don't use a direct map and explicitly call it after enumerating the available physical memory with an estimate of how much KVA we need to initialize uvm. ok patrick@
* Recognise Cortex-A65.jsg2019-06-011-1/+4
| | | | ok kettenis@
* Deimos is Cortex-A77.kettenis2019-05-311-4/+4
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* Add MSI-X support.kettenis2019-05-311-30/+40
| | | | ok patrick@
* Add MSI-X support for acpipci(4). This splits out some generic code intokettenis2019-05-314-33/+134
| | | | | | | a new pci_machdep.c file such that it can be re-used by other arm64 PCI host bridge drivers in the future. ok patrick@
* Use two 32-bit writes instead of a single 64-bit write to write thekettenis2019-05-301-2/+3
| | | | | | | | | message address into an MSI-X table entry. The RTL8168/RTL8111 hardware does not respond to 64-bit access (reads return all-ones, writes are ignored) and the PCI specification documents separate 32-bit "DWORD" fields for message address and message upper address. ok mlarkin@, jmatthew@
* On bigger arm64 machines with plenty of memory it is possible thatpatrick2019-05-284-15/+62
| | | | | | | | | | | | | | the kernel, which is allocated in low memory by efiboot, is not in the same 512 GiB L0 address space as the EFI/FDT/ACPI tables. Since we only identity-map a single L0 entry for bootstrapping purposes we can't reach those tables. Keep a set of spare L1 tables, currently one, which we can dynamically enter into the identity map so that we are able to reach those tables. While there, do the FDT mapping a bit later in C code by calling pmap_map_early(). This allows us to boot further on Packet's Ampere eMAGs. Discussed with drahn@ ok kettenis@
* Correct the test for when the L1TF vulnerablity has been mitigated viaguenther2019-05-281-4/+9
| | | | | | | either hardware update (RDCL_NO) or our being nested in a VM which is handling the flushing via the L1D_FLUSH MSR. ok mlarkin@
* Skip doing MDS mitigation on vmm entry if the new firmware is present,guenther2019-05-281-5/+14
| | | | | | as it enhances the L1D_FLUSH MSR to flush MDS too ok mlarkin@
* Cleanup some bootloader codemlarkin2019-05-281-27/+22
| | | | | | | | | Refactoring to remove 'long_kernel' variable and consistent use of 'entry' and 'marks[MARK_ENTRY]'. Prompted by guenther@. No functional change. tested by jca@ and myself ok guenther@, kettenis@
* Enable virtio again since the compilation problems have been fixed.sf2019-05-281-8/+8
| | | | ok deraadt@
* Remove a 15 year old XXX commentmlarkin2019-05-281-2/+1
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* disable virtio. a serially careless & procedure violating developerderaadt2019-05-271-8/+8
| | | | | has broken the tree once again. ok kettenis
* Pass extent for prefetchable mmio. Since there is no distinction betweenkettenis2019-05-242-2/+4
| | | | | | | prefetchable and "normal" mmio at the host bridge level we can simply pass the same extent. ok patrick@
* zap reference to non-existent function in a commentjasper2019-05-232-10/+4
| | | | ok mpi@
* Don't print "not conigured" messages for nodes that are disabled.kettenis2019-05-231-12/+13
| | | | ok patrick@
* i386/amd64 apm(4): Ignore APM_UPDATE_TIME events.cheloha2019-05-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The APM spec defines an APM_UPDATE_TIME event that is meant to cause the driver to rebase the system's wallclock against the RTC. The event itself is apparently caused by occasional blackout periods where interrupts cannot be delivered, which might cause the system to miss a tick. The problem is that on systems where these events are frequent this constantly erodes the system wallclock. The RTC is not the greatest clock in the world so these systems are always playing catch-up. ntpd(8) is a far better clock corrector than rebasing against the RTC, so it should be safe to simply ignore the event. We continue to record the event for userspace listeners, but we do not call inittodr(9) on receipt of the event. Linux has ignored the event since v2.6.21: https://github.com/torvalds/linux/commit/c1d370e167d66b10bca3b602d3740405469383de#diff-d85b9a44da8e5dfb2fb1bcbd304c2a6c Discovered by jcs@. Discussed a bit with jcs@, tedu@, deraadt@. Fix tested by jcs@. "I think we should ignore the event" deraadt@
* Allow loading of bigger ucode. This implementation uses the UEFI memorykettenis2019-05-221-5/+12
| | | | | | | | | | allocation service to allocate a block of memory below 16MB such that there is no risk of overwriting it when the bootloader moves the kernel in place. It removes the 128k limit that was previously there. Based on an earlier diff by patrick@ ok mlarkin@
* add amdgpu from linux 4.19.44 for recent AMD Radeon partsjsg2019-05-212-3/+34
| | | | | | | committing now so this can be worked on in tree Thanks to the OpenBSD Foundation for sponsoring this work and kettenis@ for helping.
* Both FreeBSD and I appear to have been confused by intel's deep-dive doc:guenther2019-05-181-3/+2
| | | | | | | | the RDCL_NO bit of the ARCH_CAPA msr only indicates one of the MDS subissues is mitigated; only the MDS_NO bit indicates they're all mitigated. ok jsg@ mlarkin@
* Add parsing for standard boot options.visa2019-05-181-2/+28
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* Oops, forgot to include a copyright year when originally addedguenther2019-05-171-2/+2
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* Mitigate Intel's Microarchitectural Data Sampling vulnerability.guenther2019-05-1714-19/+397
| | | | | | | | | | | | | | | | If the CPU has the new VERW behavior than that is used, otherwise use the proper sequence from Intel's "Deep Dive" doc is used in the return-to-userspace and enter-VMM-guest paths. The enter-C3-idle path is not mitigated because it's only a problem when SMT/HT is enabled: mitigating everything when that's enabled would be a _huge_ set of changes that we see no point in doing. Update vmm(4) to pass through the MSR bits so that guests can apply the optimal mitigation. VMM help and specific feedback from mlarkin@ vendor-portability help from jsg@ and kettenis@ ok kettenis@ mlarkin@ deraadt@ jsg@
* Add support to the BIOS bootloader for random kernel base VAmlarkin2019-05-159-27/+380
| | | | | | | | This diff adds support to be able to load a randomly linked kernel VA (subject to some range restrictions). This change has been in snaps for a few days without any fallout. ok deraadt@
* Reduce branch emulation page access protection during setup. The setupvisa2019-05-151-3/+3
| | | | | | | stage does not need execute access, so map the page initially with read-write protection. OK miod@
* Drop redundant pmap_proc_iflush() call. The needed instruction cachevisa2019-05-151-2/+1
| | | | | | | | | | | invalidation is done by mips64 pmap when the branch emulation page is made executable. Originally, the pmap_proc_iflush() call was necessary. The instruction cache invalidation was added in pmap_protect() after the FPU emulation was introduced. OK miod@
* free(9) sizes.mpi2019-05-133-5/+10
| | | | From miod@
* Move idepth tracking out of interrupt controller into common layer.drahn2019-05-132-12/+7
| | | | 'looks good' kettenis@
* vmm: add host side pvclockpd2019-05-132-21/+89
| | | | | | | | | Emulate kvm pvclock in vmm(4). Compatible with pvclock(4) in OpenBSD. Linux does not attach to this (yet). Fixes by reyk@ and tested extensively by reyk@, tb@ and phessler@ ok mlarkin@ phessler@ reyk@
* regen (missed this when I did the colemak update)abieber2019-05-131-2/+5
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* Add the needed ICC_PMR_EL1 register bit defines for the previouspatrick2019-05-131-2/+6
| | | | | | | commit to unbreak the build. from kettenis@ ok drahn@
* Delete cpu_idle_{enter,leave}_fcn() as unused. Add RETGUARD checks toguenther2019-05-123-13/+8
| | | | | | cpu_idle_cycle() ok mpi@ kettenis@
* s/availible/available/guenther2019-05-121-2/+2
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