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* Combine octeon_pcibusvar.h into octeon_pcibus.c to reduce scatter.visa2021-03-042-56/+9
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* Update clock interrupt count atomically.visa2021-03-041-2/+4
| | | | | This avoids errors that can arise when multiple cores update the variable at the same time.
* Remove bogus (and pointless) pmap_activate(9) call.kettenis2021-03-031-3/+1
| | | | ok drahn@
* Do *not* delay while waiting for IOTLB invalidation to complete. A 1mspatrick2021-03-021-3/+1
| | | | | | | delay is awful in a hot path, and the SMMU is actually quite quick on invalidation, so simply removing the delay is worth a thousand roses. Found with mental support from dlg@ (and btrace)
* Update the MSI addresses for the Armada 8040. This chunk will only bepatrick2021-03-011-3/+7
| | | | there until we have a proper way of making the MSI pages available.
* Instead of sprinkling the device's DMA tag, always return a new DMA tagpatrick2021-03-013-41/+33
| | | | | | | | | | which is based on the IOMMU's. If you think about it, using the IOMMU's DMA tag makes more sense because it is the IOMMU that does the actual DMA. Noticed while debugging, since the SMMU's map function was called twice: once for the PCI device, and once for its ppb(4). As the transaction has the PCI device's Stream ID, not the ppb(4)'s, this would be useless work. Suggested by kettenis@
* Have acpipci(4) look for a matching SMMU in the IORT.patrick2021-02-281-1/+69
| | | | ok kettenis@
* Enable acpiiort(4), add smmu(4) but keep disabled.patrick2021-02-282-2/+8
| | | | ok kettenis@
* acpiiort(4) and smmu(4)patrick2021-02-281-1/+14
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* Add smmu(4), a driver the ARM System MMU. This IOMMU is basically apatrick2021-02-285-0/+2008
| | | | | | | | | | | | | | | | | | regular ARM CPU MMU re-used for I/O devices. Implementations can have a mix of stage-2 only and stage-2/stage-2 context blocks (domains). The IOMMU allows different ways of grouping devices into a single domain. This implementation only supports SMMUv2, since there is basically no relevant SMMUv1 hardware. It also only supports AArch64 pagetables, the same as our pmap. Hence lots of code was taken from there. There is no support for 32-bit pagetables, which would have also been needed for SMMUv1 support. I have not yet seen any machines with SMMUv3, which will probably need a new driver. There is some work to be done, but the code works and it's about time it hits the tree. ok kettenis@
* Add acpiiort(4), a driver for the ACPI I/O Remapping Table. This tablepatrick2021-02-282-0/+138
| | | | | | contains information which IOMMUs we have and how the devices are routed. ok kettenis@
* Add memory attributes for stage-2 pagetables.patrick2021-02-281-1/+7
| | | | ok kettenis@
* Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick2021-02-282-2/+9
| | | | ok kettenis@
* Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick2021-02-281-1/+8
| | | | ok kettenis@
* apldart(4) is needed here as well.kettenis2021-02-271-1/+2
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* Add apldart(4), a driver for the IOMMU on Apple M1 SoCs.kettenis2021-02-273-2/+567
| | | | ok patrick@
* Add aplcpie(4), a (minimal) driver for the PCIe host bridge on Apple M1 SoCs.kettenis2021-02-264-3/+505
| | | | ok patrick@
* Add some infrastructure in the PCI chipset tag for pci_probe_device_hook()patrick2021-02-256-8/+45
| | | | | | so that we can provide IOMMU-hooked bus DMA tags for each PCI device. ok kettenis@
* we don't have to cast to caddr_t when calling m_copydata anymore.dlg2021-02-252-8/+6
| | | | | | | | | | | | | | | | the first cut of this diff was made with coccinelle using this spatch: @rule@ type caddr_t; expression m, off, len, cp; @@ -m_copydata(m, off, len, (caddr_t)cp) +m_copydata(m, off, len, cp) i had fix it's opinionated idea of formatting by hand though, so i'm not sure it was worth it. ok deraadt@ bluhm@
* Add aplintc(4), a driver for the interrupt controller found onkettenis2021-02-234-3/+388
| | | | | | Apple M1 SoCs. ok patrick@
* sparc64/clock.c: use ANSI-style function definitionscheloha2021-02-231-57/+20
| | | | | | | | While here, zap a few ARGUSED linter comments. Compile-tested by deraadt@. ok deraadt@
* Make more efficient clearing interrupts on all processors at boot time.aoyama2021-02-231-4/+4
| | | | | | | | | | | | | | | | Without this modification, because of the volatile qualifier, the compiler does not produce four `` = 0 '' assignments, but code equivalent to: *(volatile uint32_t *)INT_ST_MASK3 = 0; *(volatile uint32_t *)INT_ST_MASK2 = *(volatile uint32_t *)INT_ST_MASK3; *(volatile uint32_t *)INT_ST_MASK1 = *(volatile uint32_t *)INT_ST_MASK2; *(volatile uint32_t *)INT_ST_MASK0 = *(volatile uint32_t *)INT_ST_MASK1; Anders Gavare reported to Miod Vallat, and he gave me a diff.
* remove some unused includesjsg2021-02-234-198/+0
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* timecounting: use C99-style initialization for all timecounter structscheloha2021-02-2319-70/+176
| | | | | | | | | | | | | | | | | | The timecounter struct is large and I think it may change in the future. Changing it later will be easier if we use C99-style initialization for all timecounter structs. It also makes reading the code a bit easier. For reasons I cannot explain, switching to C99-style initialization sometimes changes the hash of the resulting object file, even though the resulting struct should be the same. So there is a binary change here, but only sometimes. No behavior should change in either case. I can't compile-test this everywhere but I have been staring at the diff for days now and I'm relatively confident this will not break compilation. Fingers crossed. ok gnezdo@
* Terminate backtrace of secondary processors in ddb.kettenis2021-02-221-1/+4
| | | | From miod@
* Enable bge(4).kettenis2021-02-222-2/+4
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* Enable apldog(4).kettenis2021-02-223-3/+9
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* Add apldog(4), a driver for the watchdog on Apple M1 SoCs.kettenis2021-02-221-0/+117
| | | | | | This allows us to reboot the machine. ok patrick@
* Add cryptox(4), a driver for armv8 cryptographic extensions.tobhe2021-02-215-3/+1660
| | | | | | | | The driver currently only supports AES-CBC mode but can easily be extended to other algorithms and modes. The aesv8-armx.S file was generated from the CRYPTOGAMS project. Asked to commit by and ok patrick@
* One CPUs that implement the VHE extension and have the E2H bit set, keepkettenis2021-02-212-6/+12
| | | | | | running the kernel in EL2. ok patrick@
* Fix disestablishing of PCI interrupt handlers.visa2021-02-201-9/+2
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* Make kernel ld.script similar to octeon's on loongson and sgi.visa2021-02-182-14/+74
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* handle "simple-pm-bus" in simplebusjsg2021-02-181-5/+10
| | | | | | | Enables a clock and/or power domain for a group of devices. Required to use linux 5.11 dtbs on am335x and omap4. ok kettenis@
* Skip gp initialization in loongson bootblocksvisa2021-02-172-3/+1
| | | | | | | The loongson bootblocks are compiled with -mno-abicalls and do not use gp-relative addressing. A similar change has been made to the mips64 kernels recently.
* Do not reprogram address filter after MII status changevisa2021-02-171-5/+1
| | | | | The address filter is not affected by link parameter changes, so its reprogramming can be skipped.
* Add support for FIQs. We need these to support agtimer(4) on Apple M1 SoCskettenis2021-02-179-49/+104
| | | | | | | | since its interrupts seem to be hardwared to trigger an FIQ instead of an IRQ. This means we need to manipulate both the F and the I bit in the DAIF register when enabling and disabling interrupts. ok patrick@
* Introduce BUS_SPACE_MAP_POSTED such that we can distinguish betweenkettenis2021-02-168-31/+43
| | | | | | | | posted and non-posted device memory mappings and set the right memory attributes for them. Needed because on the Apple M1 using the wrong mapping will fault. ok patrick@, dlg@
* some phy are not needed anymore since the ethernet drivers went awayderaadt2021-02-161-6/+6
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* While it should be possible to use "normal uncachable" mappings forkettenis2021-02-151-1/+2
| | | | | | | | write-combining on arm64 as Linux does, this doesn't seem to work on NXP's LX2160A SoC. So switch to using "device" mappings for now to make amdgpu(4) work better. ok patrick@
* Enable clocks and adjust for removal of subnodes in upstream Linuxkettenis2021-02-141-2/+4
| | | | device trees.
* Enable clocks.kettenis2021-02-141-1/+4
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* Raise match priority to beat syscon(4).kettenis2021-02-141-39/+81
| | | | | | | Use the right clock for the Cortex-A7 cores. Support CPU clocks and remove exclock_cpuspeed(). ok patrick@
* Recent device trees have the syscon-reboot and syscon-poweroff nodes askettenis2021-02-142-11/+22
| | | | | | | children of the node claimed by expower(4). That node also fained a "syscon" compatible in the process. Deal with these changes, ok patrick@
* Revise cnmac(4)'s address filter setupvisa2021-02-134-114/+47
| | | | | | | | | Set up the DMAC filter in one go instead of doing it separately for unicast and multicast DMACs. This attempts to make the code a little more readable. The setup should now run a bit faster as well because it now does fewer register accesses. Tested on CN5020, CN6120 and CN7130.
* Fix a commentmlarkin2021-02-131-2/+2
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* Remove trailing whitespacemlarkin2021-02-131-14/+14
| | | | No code/functional change
* Remove trailing whitespacemlarkin2021-02-131-6/+6
| | | | No code/functional change
* Call exuart(4) early attach on arm64.patrick2021-02-111-1/+3
| | | | ok kettenis@
* Enable exuart(4).patrick2021-02-112-2/+8
| | | | ok kettenis@
* Leave out gp initialization from kernel entry on mips64visa2021-02-119-24/+8
| | | | | | | | | On OpenBSD/mips64, the kernel is compiled with -mno-abicalls. This disables gp-relative addressing and essentially makes gp a spare register in the kernel. Hence it is unnecessary to initialize gp when entering the kernel. The _gp symbol is not needed either. Suggested by miod@
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